Leakage Compensated Reference Voltage for E-Fuse Sense Circuits
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Solution Overview
Problem
The existing single-ended sense scheme for electrical fuses in semiconductor chips is prone to sensing errors due to leakage current from unselected bitcells, which reduces the signal margin and is sensitive to programming patterns and manufacturing process variations.
Innovation Solution
A sense circuit with a reference voltage generator that compensates for leakage current by using a leakage-path simulation structure and adjusting the AC impedance, offsetting the reference voltage to balance '1' and '0' margin levels, thereby enhancing the signal margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single-ended sense scheme is used for electrical fuses, then the circuit area is reduced, but the signal margin decreases due to leakage current from unselected bitcells
Solution Approach 1:
The sense amplifier is divided into two symmetric halves, each handling one polarity of the differential signal. This segmentation allows each half to be optimized for detecting its specific signal level while being less sensitive to leakage from unselected bitcells, thereby maintaining signal margin without increasing overall circuit area.
Solution Approach 2:
A virtual ground node is introduced as an intermediary reference point in the differential sense scheme. This virtual ground acts as a stable reference that isolates the sensing operation from leakage currents in unselected bitcells, enabling reliable detection while maintaining compact circuit area.
2Measurement precision
If the reference voltage is set halfway between '1' and '0' bitline levels, then equal sense margin is achieved for both states, but leakage current from unselected bitcells shifts the voltage levels and reduces the sense margin
Solution Approach 1:
The differential sense amplifier maintains symmetric voltage levels around a virtual ground, creating equipotential conditions for both '0' and '1' states. This symmetry ensures that leakage currents affect both differential inputs equally, canceling out their impact on the sense margin and maintaining equal detection capability for both states.
Solution Approach 2:
The sense amplifier employs positive feedback through cross-coupled transistors that amplify the differential voltage between the two bitline inputs. This feedback mechanism enhances the small voltage differences caused by fuse resistance changes, improving measurement precision while the differential structure inherently compensates for leakage effects.
3Quantity of substance
If multiple electrical fuses share a common bitline in an array format, then the device density is increased, but the leakage current from unselected fuses affects the sensing accuracy of selected fuses
Solution Approach 1:
The bitline array is segmented into multiple independent differential sense amplifiers, each handling a specific subset of fuses. This segmentation isolates the sensing operation for selected fuses from leakage currents in unselected fuses on the same physical bitline, maintaining high device density while improving sensing accuracy through electrical isolation.
Solution Approach 2:
Virtual ground nodes serve as intermediaries between different fuse groups sharing common bitlines. These virtual grounds provide stable reference potentials that prevent leakage currents from propagating between different fuse groups, enabling accurate sensing in high-density array configurations.
Data Source
AI summary
An e-fuse sense circuit employs a single ended sense scheme in which the reference voltage is compensated for leakage. A reference voltage generator includes a pull-up resistor of similar value to the selected bitline pull-up resistor. As the sensing trip point is adjusted by selection of a bitline pull-up resistor, a pair of pull-up and pull-down resistors are adjusted together to adjust the impedance of the reference voltage generator. A leakage-path simulation structure including a parallel connection of bitcells is added to the reference voltage generator. The leakage-path simulation structure imitates the bitcells on a bitline in the array of e-fuses. Leakage current on the bitline offsets the bitline voltage by a certain error voltage. The reference voltage is also offset by a fraction of the error voltage to balance the shifts in the ‘1’ and ‘0’ margin levels in the presence of leakage.