Leakage Current Compensation Circuit for Memory Read Reliability
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Solution Overview
Problem
Next-generation memory devices face challenges in improving read operation reliability due to leakage currents from unselected memory cells, which affect sensing margins and read windows, leading to increased errors and reduced performance.
Innovation Solution
Incorporating a leakage current compensation circuit that compensates for the total leakage current generated by unselected memory cells during read operations, ensuring a wider read window and sensing margin by connecting to either local or global word lines and bit lines, and using transistors to mirror the current and discharge effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read operation is performed in a memory device, then data can be read from selected memory cells, but leakage currents from unselected memory cells reduce read operation reliability and sensing margins
Solution Approach 1:
The patent extracts the harmful leakage current from unselected memory cells by introducing a compensation circuit that specifically targets and removes this unwanted current component. The compensation circuit is connected to the word line and actively subtracts the leakage current contribution, isolating the signal from selected cells from the harmful background current.
Solution Approach 2:
The patent implements a feedback mechanism where the compensation circuit continuously monitors and adjusts for leakage current effects during read operations. By using the same word line that carries the signal to also carry the leakage current information, the system creates a feedback loop that enables real-time compensation, improving read reliability without adding separate sensing paths.
2Reliability
If leakage current compensation is implemented, then read operation reliability improves, but device complexity increases due to additional compensation circuits
Solution Approach 1:
The compensation circuit is designed to serve multiple functions: it compensates for leakage current during read operations, maintains word line voltage stability, and works across different memory cell configurations. By making the compensation circuit universal rather than specialized for a single function, the patent reduces overall device complexity while achieving reliability improvements.
Solution Approach 2:
The compensation circuit utilizes existing circuit elements and signals within the memory device to perform leakage current compensation. By leveraging the word line itself and existing transistor structures, the circuit serves itself rather than requiring entirely separate compensation mechanisms, thereby minimizing the increase in device complexity.
3Measurement precision
If compensation current is applied to counteract leakage current, then sensing margin increases, but power consumption increases due to additional current flow
Solution Approach 1:
The patent applies partial compensation rather than attempting to counteract all current flow. The compensation circuit is designed to provide just enough current to offset the leakage effect and maintain adequate sensing margins, rather than using excessive compensation current. This partial action approach achieves the necessary precision improvement while minimizing additional power consumption.
Solution Approach 2:
The compensation circuit dynamically adjusts compensation current parameters based on operating conditions. By changing current magnitude and timing parameters rather than maintaining constant high-level compensation, the system achieves improved sensing margins while reducing overall power consumption compared to fixed high-power compensation schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces reading errors by securing a wider read window and sensing margin, thereby enhancing the reliability and performance of read operations in memory devices.
Implementation Method 1
a leakage current compensation circuit connected to a selected word line path from the selected memory cell to the sense amplifier, and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode
Implementation Method 2
a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage
Implementation Method 3
the local word line select transistor configured to selectively form an electrical flow path between the selected memory cell and a selected global word line from among the plurality of global word lines
Implementation Method 4
a discharge transistor connected to one end of the sense amplifier and configured to discharge a charge of the selected word line in the read operation mode of the memory device
Data Source
AI summary
A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.