Leakage-Current Data Retention Circuit for Low-Power Sleep Mode

The patent changes the voltage parameter by allowing the supply voltage to drop to a lower retention voltage level during sleep mode. The circuit is designed to maintain data retention functionality at this reduced voltage level, directly reducing power consumption while preserving the essential data retention capability. This is achieved through careful design of the latch circuit and transistor sizing to ensure proper operation at the reduced voltage.

The patent extracts and eliminates unnecessary leakage current paths from the conventional master-slave flip-flop circuit. By removing redundant transistors and optimizing the circuit topology, the design reduces leakage current consumption while maintaining data retention functionality, directly addressing the high power consumption issue during sleep mode.

The patent implements periodic action by using leakage current recycling mechanisms that periodically recharge the retention node during sleep mode. Instead of continuous power supply, the circuit utilizes the natural leakage currents flowing through the transistors and recycles them to maintain the retained data state, converting a continuous energy loss into a periodic self-sustaining process.

The circuit employs self-service mechanisms where the leakage currents that would normally represent energy loss are instead harnessed and recycled to maintain the retained data. The transistor leakage currents are directed to recharge the retention node, allowing the circuit to sustain itself using its own internal leakage currents without requiring continuous external power supply.