Leakage Compensation Delay Circuit for ADC Clock Skew
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Solution Overview
Problem
In analog-to-digital converter (ADC) circuits, switch leakage currents cause voltage droop across capacitors, leading to clock time skew, which is particularly problematic in low-speed interleaved ADC operations and across varying clock frequency ranges, process, voltage, and temperature conditions.
Innovation Solution
A switch leakage compensation delay circuit is introduced, featuring a compensating transistor that bypasses leakage current around a capacitor, maintaining voltage across the capacitor constant by matching the leakage current provided by the control transistor, thereby reducing clock time skew. This circuit includes a compensating transistor connected in parallel with the control transistor, with its gate tied to its source and the second node, ensuring the voltage remains constant when the control transistor turns off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a control transistor is used to switch a capacitor in an ADC circuit, then the circuit can operate with digital control signals, but leakage current from the transistor causes voltage droop across the capacitor
Solution Approach 1:
A compensating transistor is introduced as an intermediary element connected in parallel with the control transistor. This compensating transistor acts as a mediator that supplies leakage current to counterbalance the leakage current from the control transistor, thereby maintaining voltage stability across the capacitor while preserving digital control capability
Solution Approach 2:
The harmful leakage current from the control transistor is converted into a beneficial effect by introducing a compensating transistor that generates an equal and opposite leakage current. The two leakage currents cancel each other out, transforming the original harmful leakage into a useful voltage-stabilizing mechanism
2Use of energy by moving object
If the control transistor is turned off to stop signal flow, then power consumption is reduced, but leakage current causes voltage droop that affects timing accuracy
Solution Approach 1:
When the control transistor is turned off to reduce power consumption, its leakage current (which would normally be harmful) is compensated by the compensating transistor. The compensating transistor's leakage current benefits the system by maintaining capacitor voltage, thereby preserving timing accuracy even during low-power operation
3Reliability
If a traditional leakage compensation method is used with separate compensation circuits, then voltage droop can be corrected, but circuit complexity and area increase
Solution Approach 1:
The compensating transistor is merged with the control transistor by connecting them in parallel between the same nodes. This merging approach allows the compensation function to be integrated into the existing switch structure, avoiding additional separate compensation circuits and reducing overall circuit complexity while maintaining voltage stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates voltage droop and reduces clock time skew, enabling ADC operation across large clock frequency ranges and varying conditions without demerits, while also reducing fabrication steps, area, and power consumption, and allowing for reconfigurability in programmable logic like FPGAs or fixed hardware like ASICs.
Implementation Method 1
a leakage current of the control transistor may be supplied from a leakage current of the compensating transistor such that the voltage across the capacitor may be maintained substantially constant
Data Source
AI summary
Apparatus and associated methods relating to a switch leakage compensation delay circuit include a compensating transistor configured to passively bypass a leakage current around a capacitor that connects in series with a control transistor. In an illustrative example, the capacitor and the compensating transistor may be connected in parallel between a first node and a second node. The compensating transistor gate may be tied, for example, directly to its source and to the second node. The control transistor may connect its drain to the second node. When a control signal turns off the control transistor, a leakage current of the control transistor may be supplied from a leakage current of the compensating transistor such that the voltage across the capacitor may be maintained substantially constant. The delay circuit may advantageously mitigate the capacitor's voltage droop to reduce clock time skew, for example, in low speed interleaved ADC operation.