Leakage Current Detection Circuit for Memory Die Area Reduction

The detection circuit performs multiple functions: it detects leakage current, identifies defect types (word line to word line shorting, word line to substrate shorting), and provides test results all through a single integrated circuit structure. This multi-functionality eliminates the need for separate dedicated detection circuits for each function, thereby reducing overall die area while maintaining comprehensive detection capability.

The detection circuit employs a nested structure where the test signal generation circuit, leakage current measurement circuit, and control logic are integrated within a compact footprint. The circuit uses shared components such as a common test signal line that serves multiple word lines sequentially, and a unified detection mechanism that analyzes current characteristics to identify different defect types, thereby minimizing the space required for each functional element.

The detection process is segmented into distinct phases: test signal application phase, leakage current measurement phase, and defect identification phase. The circuit is divided into functional modules: test signal generation unit, leakage current measurement unit, and control logic unit. Each module handles a specific aspect of defect detection, making the overall system more manageable and less complex while maintaining comprehensive detection capability for various defect types.

The detection circuit uses an intermediary measurement mechanism that converts complex defect detection into a simplified electrical measurement problem. By injecting a controlled test signal and measuring the resulting leakage current characteristics, the circuit indirectly identifies defect types without requiring direct physical inspection or complex analysis. This intermediary approach simplifies the detection logic while maintaining high reliability in defect identification.