Leakage Power Optimization for Digital Integrated Circuits
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Solution Overview
Problem
Existing machine learning-based methods for leakage power optimization in digital integrated circuits fail to achieve high-accuracy predictions and efficiently optimize leakage power due to the inability to distinguish different adjacent gate cells and loss of topological information, leading to prolonged design cycles and increased time consumption.
Innovation Solution
A multi-step optimization method involving the extraction of topological connection information, feature matrices, and path features, followed by training with a graph neural network, bi-directional long short-term memory network, and artificial neural network to predict suitable voltage thresholds for gate cells, merging outputs to a voltage threshold classification network for accurate leakage power optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If voltage threshold adjustment is performed to optimize leakage power, then leakage power is reduced, but timing constraints may be violated and design time is prolonged
Solution Approach 1:
The patent applies preliminary action by pre-extracting topological connection information, timing features, and power features before optimization. A graph neural network is trained in advance to predict optimal voltage thresholds, enabling rapid inference during the actual optimization process without repeated iterative checks
Solution Approach 2:
The patent replaces the traditional iterative mechanical optimization process with a machine learning-based prediction system. Instead of repeatedly adjusting voltage thresholds and checking timing constraints through iterative simulations, the system uses a trained graph neural network to directly predict optimal voltage assignments based on topological and feature data
2Productivity
If traditional machine learning methods are used for leakage power optimization, then optimization speed is improved, but prediction accuracy deteriorates due to inability to capture topological information
Solution Approach 1:
The patent applies dimensionality change by transitioning from node-only features to graph-level topological information. The graph neural network operates on the circuit topology structure, capturing relationships between adjacent gate cells and paths that traditional node-based methods miss, thereby improving prediction accuracy while maintaining speed
Solution Approach 2:
The patent uses composite materials by combining multiple types of information: topological connection information, timing features, and power features. The graph neural network integrates these heterogeneous data sources to create a comprehensive prediction model that achieves both high accuracy and efficient optimization
3Measurement precision
If graph neural network is used to capture topological information, then prediction accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the computational task into distinct phases: pre-processing feature extraction, graph neural network training, and inference. The graph neural network processes information in layers, with each layer capturing topological information at different granularities, making the complex computation manageable and efficient
Data Source
AI summary
An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.