Leakage Reduction Circuit for Memory Arrays
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Solution Overview
Problem
Large memory arrays, such as SRAM and CRAM, experience significant leakage current due to biased NMOS or PMOS transistors during idle states, leading to increased power consumption and performance limitations in integrated circuits.
Innovation Solution
A leakage reduction circuit that intelligently biases bit lines based on the majority state of memory cells, using a frame bias signal to selectively charge bit lines during idle states, thereby reducing the number of leakage paths and minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are biased during idle states to maintain memory cell states, then memory function is preserved, but leakage current increases
Solution Approach 1:
The patent applies local quality by differentiating the biasing approach for different bit lines based on the majority state of memory cells in each frame. Instead of uniformly biasing all bit lines, the system selectively biases bit lines according to the specific majority state (0 or 1) of each frame, thereby reducing leakage current in frames where biasing is not needed while maintaining functionality where required.
Solution Approach 2:
The patent implements dynamics by making the bit line biasing strategy adaptive and configurable based on the programmed state of memory cells. The system dynamically determines the majority state of each frame and adjusts the biasing behavior accordingly, transitioning between biasing and non-biasing states based on actual memory content rather than using a fixed approach.
2Reliability
If all bit lines are biased to maintain memory states, then memory reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by biasing only the necessary bit lines based on the majority state of each frame, rather than biasing all bit lines uniformly. This selective approach ensures that power is consumed only when and where needed to maintain memory states, avoiding excessive power consumption from biasing bit lines that do not require it.
Solution Approach 2:
The system implements local quality by tailoring the biasing strategy to the specific characteristics of each frame's memory cell states. Each frame is evaluated independently to determine its majority state, and biasing is applied locally to only those bit lines that correspond to frames requiring state maintenance, thereby optimizing power consumption across the entire memory array.
3Use of energy by moving object
If frame bias signal is implemented to reduce leakage, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the leakage reduction circuit to perform multiple functions: determining the majority state of memory cells in each frame, generating appropriate frame bias signals, and controlling bit line biasing. This multi-functional approach consolidates what could be separate complex components into a unified circuit that handles state detection, signal generation, and control in one integrated structure.
Solution Approach 2:
The leakage reduction circuit implements self-service by automatically detecting the majority state of memory cells and autonomously determining the appropriate biasing strategy without external intervention. The circuit monitors the programmed states of memory cells, calculates the majority state for each frame, and independently generates the necessary frame bias signals, reducing the need for additional external control mechanisms.
Data Source
AI summary
Disclosed are apparatus and devices for programming and operating a programmable memory array portion coupled with a leakage reduction circuit. At the leakage reduction circuit, a frame bias signal that indicates a majority state of the memory array portion can be received. During idle states of the programmable memory array portion, at least one shared bit line of the memory array portion can be selectively biased based on the received frame bias signal. In one aspect, a first one of two bit lines is biased to a first state, while the second one of the two bits lines is biased to a second state that is opposite the first state. In a further aspect, the first state is a same state as the majority state of the memory array portion.