Leakage Current Sensing Unit for Variable Resistive Memory Read Errors

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Solution Overview

Problem

Next-generation memory devices face challenges with leakage currents, which cause set/reset determination errors in variable resistive memory devices, limiting their performance and reliability.

Innovation Solution

A semiconductor integrated circuit device with a leakage current sensing unit and a determination circuit unit that measures and compensates for leakage currents, allowing for accurate data state determination by comparing voltage levels and currents, thereby reducing read errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If variable resistive memory devices are used to achieve large capacity and ultra-high speed, then storage capacity and speed are improved, but leakage currents cause set/reset determination errors

Engineering Contradiction:
Improvestorage capacity and speedVSAvoidset/reset determination accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by measuring the leakage current of the resistive memory device before performing the set/reset operation. The leakage current measurement is conducted in advance using a dedicated sensing unit, and this measured value is stored for later compensation during the actual set/reset determination process, thereby eliminating the harmful effect of leakage currents on determination accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the measured leakage current value to compensate for the leakage current effect during set/reset determination. The leakage current sensing unit continuously monitors and provides feedback on the leakage current state, allowing the determination circuit to adjust its operation based on the actual leakage conditions, thus maintaining high determination accuracy despite the presence of leakage currents.

Inventive Principle:
Principle #23Feedback

2Reliability

If leakage current sensing unit is added to compensate for leakage currents, then determination accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvedetermination accuracyVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the leakage current sensing unit to serve multiple functions: it measures leakage current for compensation, monitors device health status, and provides data for optimization algorithms. This multi-functional approach reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity while maintaining high determination accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements self-service by enabling the resistive memory device to self-measure and self-compensate for leakage currents using integrated sensing units and optimization algorithms. The device autonomously monitors its own leakage characteristics and adjusts operations accordingly, eliminating the need for external complex measurement and compensation systems, thus improving determination accuracy without proportionally increasing overall device complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9460786B2Semiconductor integrated circuit device including a leakage current sensing unit and method of operating the same
Publication Date: 2016.10.04 SK HYNIX INC
  • US9460786B2 patent drawing
  • US9460786B2 patent drawing
  • US9460786B2 patent drawing

AI summary

A semiconductor integrated circuit device configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The semiconductor integrated circuit device may include a leakage current sensing unit configured for sensing a pure leakage current of a cell array, and a determination circuit unit configured for comparing a voltage level of the input node with a reference voltage and for determining a state of read data while in a read mode. Whereby an output current may be compared with a read current of the cell array at the input node, and the output current may include the summation of the pure leakage current and a reference current.