Lean Multi-Plane NAND Read Sequence Without Column or Busy Cycles
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Solution Overview
Problem
NAND-type flash memory operations face increased latency and performance issues due to command overhead, including dummy busy cycles and column address cycles, which are not scalable with increasing input/output speeds.
Innovation Solution
A 'super lean' read command sequence is implemented that eliminates column address cycles, multi-plane confirm commands, and dummy busy cycles, optimizing data transfer by using a fixed column address and streamlined command protocol for multi-plane read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional command sequences with dummy busy cycles and column address cycles are used, then complete data transfer is achieved, but command latency increases and performance deteriorates
Solution Approach 1:
The patent extracts and removes unnecessary command elements (dummy busy cycles and column address cycles) from the traditional read command sequence. By eliminating these redundant components, the command latency is reduced significantly while maintaining complete data transfer functionality, directly resolving the contradiction between time loss and productivity.
Solution Approach 2:
The patent changes the parameter of command sequence structure by transitioning from a traditional sequence including dummy busy cycles and column address cycles to a streamlined sequence without these elements. This parameter change enables faster command execution while preserving data integrity, thereby reducing latency without sacrificing read operation efficiency.
2Reliability
If multiple dummy busy cycles are included for multi-plane confirm commands, then data transfer completeness is ensured, but command overhead increases and scalability decreases
Solution Approach 1:
The patent extracts and removes dummy busy cycles and multi-plane confirm commands from the command sequence. This extraction eliminates unnecessary complexity while maintaining data transfer completeness through alternative mechanisms, directly addressing the contradiction between reliability and device complexity.
Solution Approach 2:
Instead of using traditional confirm commands with dummy busy cycles to ensure data transfer completeness, the patent inverts the approach by using a streamlined command sequence that achieves completeness through efficient data readout operations, thereby reducing command sequence complexity while maintaining reliability.
3Measurement precision
If column address cycles are transmitted for each read operation, then precise column access is achieved, but command overhead increases and performance scalability is limited
Solution Approach 1:
The patent extracts and removes column address cycles from the read command sequence. By eliminating this redundant addressing mechanism, the patent achieves precise column access through alternative methods while significantly reducing command overhead, thereby resolving the contradiction between measurement precision and productivity.
Solution Approach 2:
The patent applies a universal read command structure that can access multiple columns without requiring individual column address cycles for each operation. This multi-functional approach maintains precise column access capability while improving read operation speed and scalability by reducing repetitive addressing overhead.
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.