LED Array Fabrication via Inverted N-P Layer Sequence

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Solution Overview

Problem

The conventional light emitting diode (LED) array fabrication process is complicated due to the poor lateral conductivity of p-type semiconductor materials, requiring damaging processes like substrate polishing or laser lift-off to achieve an n-side up structure, which affects electrical connections and manufacturing complexity.

Innovation Solution

A method involving a temporary substrate for forming light emitting stacks with insulating and metal connecting layers, allowing for vertical or horizontal electrical connections without damaging the substrate, enabling a simpler and more reliable fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If substrate polishing or laser lift-off is used to achieve n-side up structure, then the electrical connection is improved, but the manufacturing complexity and damage to electrical connection increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent inverts the conventional n-side down structure to an n-side up structure by forming the n-type semiconductor layer above the p-type semiconductor layer, eliminating the need for substrate polishing or laser lift-off processes. This inversion allows direct wire bonding to the n-type layer without damaging the electrical connection, thereby improving reliability while reducing fabrication complexity

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent performs preliminary actions by forming the n-type semiconductor layer and creating wire bonding pads on the n-type layer before completing the full device structure. This allows electrical connections to be established early in the fabrication process, avoiding the need for subsequent damaging substrate modification steps

Inventive Principle:
Principle #10Preliminary action

2Reliability

If p-type semiconductor layer is used with poor lateral conductivity, then the LED structure is formed, but the electrical connection efficiency deteriorates

Engineering Contradiction:
ImproveLED structureVSAvoidelectrical connection efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent inverts the conventional layer sequence by placing the n-type semiconductor layer above the p-type semiconductor layer. This inversion allows the n-type layer, which has better lateral conductivity, to serve as the electrical connection layer, thereby reducing energy loss while maintaining the LED structure

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent applies local quality by creating specific regions with different properties: the n-type semiconductor layer is positioned where electrical connection is needed to provide good lateral conductivity, while the p-type semiconductor layer maintains its light-emitting function. This localized optimization of material properties improves overall electrical connection efficiency

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If conventional horizontal electrical structure is used, then the fabrication process is simplified, but the lateral conductivity requirement increases

Engineering Contradiction:
Improvefabrication processVSAvoidlateral conductivity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent inverts the electrical connection architecture from horizontal to vertical by forming the n-type semiconductor layer above the p-type layer. This allows wire bonding to be performed vertically on the n-type layer surface, maintaining fabrication simplicity while eliminating the need for good lateral conductivity in the p-type layer

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS8421095B2Light-emitting diode array
Publication Date: 2013.04.16 ENNOSTAR CORP
  • US8421095B2 patent drawing
  • US8421095B2 patent drawing
  • US8421095B2 patent drawing

AI summary

A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack.