Low Z-Height LED Array Package With TSV Support Structure

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Solution Overview

Problem

Existing solutions for densely packed light-emitting diodes (LEDs) face challenges in providing reliable interconnections and adequate heat removal, particularly when each LED must be separately addressable, often requiring expensive materials and complex processing, and are prone to failure due to thermal expansion issues between ceramic and organic materials.

Innovation Solution

A packaging structure for light emitter pixel arrays using an inorganic substrate with through silicon vias (TSV) and a redistribution layer, which includes a top and bottom redistribution layer with copper posts for electrical connection, and a light confinement structure with phosphor and diffuser materials, allowing for dense interconnects and effective thermal transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If individual LEDs are mounted on ceramic substrate with extensive fan-in/fan-out structures and vias, then separate addressability of each LED is achieved, but device complexity and manufacturing cost increase significantly

Engineering Contradiction:
Improveseparate addressabilityVSAvoidfan-in/fan-out structures
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent transitions from planar fan-in/fan-out routing to three-dimensional vertical interconnection through TSVs. Electrical connections are routed vertically through the substrate thickness rather than spreading laterally, enabling dense pixel arrays with simplified interconnect architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention changes the interconnection topology from two-dimensional surface routing to three-dimensional volumetric routing. This parameter change in spatial dimensionality allows each pixel to be independently addressed through vertical TSV pathways without requiring extensive lateral trace networks.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ceramic substrate is used for LED mounting, then mechanical support and electrical interconnection are provided, but thermal expansion mismatch causes trace interconnect failure

Engineering Contradiction:
Improveinterconnect reliabilityVSAvoidthermal expansion mismatch
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent employs a homogeneous silicon substrate for both mechanical support and electrical interconnection, eliminating the CTE mismatch problem between dissimilar materials. The silicon substrate provides unified thermal and mechanical properties throughout the device structure.

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

The invention uses composite material architecture where silicon substrate integrates multiple functions (mechanical support, electrical interconnection, thermal management) that were previously distributed across multiple materials (ceramic substrate, organic PCB, underfill). This material integration eliminates interfacial thermal expansion mismatches.

Inventive Principle:
Principle #40Composite materials

3Productivity

If densely packed LED arrays are formed, then light emission density increases, but heat removal becomes difficult

Engineering Contradiction:
Improvelight emission densityVSAvoidheat removal
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The silicon substrate acts as an intermediary thermal management component, providing direct thermal pathways from the LED active regions to heat sinks. The high thermal conductivity of silicon enables efficient heat evacuation from densely packed pixels without requiring complex thermal interface structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Ease of operation

If small electrical traces and extensive fan-in structures are used for addressable pixels, then each LED can be separately controlled, but manufacturing cost and processing complexity increase

Engineering Contradiction:
Improveseparate addressabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The patent employs three-dimensional vertical interconnection through TSVs to replace two-dimensional lateral routing. This dimensional transition reduces the total trace length and interconnect complexity, thereby lowering manufacturing cost and processing requirements while maintaining full pixel addressability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables reliable, dense electrical connections and efficient heat management, allowing for separately addressable LEDs with improved thermal transfer characteristics, reducing the risk of thermal expansion-related failures and enabling thin, non-bulky lighting modules suitable for adaptive lighting applications.

Implementation Method 1

at least one through silicon via containing an electrical conductor is defined to pass through the inorganic substrate and support an electrical connection with the top redistribution layer

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

An inorganic substrate having a top redistribution layer is attached to the plurality of pixels... allowing for dense interconnects and effective thermal transfer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentEP3968373A1Low z-height LED array package having TSV support structure
Publication Date: 2022.03.16 LUMILEDS LLC
  • EP3968373A1 patent drawingFigure 1
  • EP3968373A1 patent drawingFigure 2
  • EP3968373A1 patent drawingFigure 3A~3B

AI summary

A packaging structure for a light emitter pixel array includes a plurality of pixels, with at least some pixels laterally separated from each other with a pixel light confinement structure. An inorganic substrate having a top redistribution layer is attached to the plurality of pixels and at least one through silicon via containing an electrical conductor is defined to pass through the inorganic substrate and support an electrical connection with the top redistribution layer.