Crack-Tolerant Dielectric Barrier for LED Thermal Stress
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Solution Overview
Problem
Semiconductor LEDs face reliability issues due to cracking in dielectric barrier layers caused by thermal stress during manufacturing, which can lead to metal migration and yield loss, particularly during the die attach process where coefficient of thermal expansion mismatches occur.
Innovation Solution
A thermally robust reflective barrier structure is introduced, incorporating a dielectric material with stress-reducing features such as trenches and crack-reducing interlayers to decouple stress and prevent crack propagation, ensuring the dielectric barrier layer's integrity and preventing metal migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric barrier layer is used to prevent metal migration, then metal migration is reduced, but the layer is susceptible to cracking due to thermal stress
Solution Approach 1:
The dielectric barrier layer is segmented into multiple sub-layers (first dielectric layer, second dielectric layer, third dielectric layer) with intermediate layers between them. This segmentation allows each layer to independently manage stress, preventing crack propagation through the entire barrier structure while maintaining metal migration prevention capability.
Solution Approach 2:
The barrier structure uses composite materials with different properties - the dielectric layers provide electrical insulation and metal migration prevention, while the intermediate layers (such as stress relief layers or materials with different CTE) provide thermal stress management. This composite approach resolves the contradiction between metal migration prevention and crack resistance.
2Ease of operation
If die attach metals are directly on the dielectric layer, then electrical connection is achieved, but thermal stress causes cracking in the dielectric layer
Solution Approach 1:
An intermediate layer is introduced between the die attach metals and the dielectric barrier layer. This intermediary layer acts as a buffer that reduces thermal stress transmission to the dielectric layer during heating/cooling cycles, preventing cracks while allowing the die attach metals to maintain direct electrical connection to the underlying structures.
Solution Approach 2:
The intermediate layer is designed with specific material parameters (such as intermediate CTE value between metal and dielectric, appropriate thickness, and mechanical compliance) that change the stress distribution parameters. This allows the dielectric layer to withstand thermal cycling without cracking while maintaining effective electrical connection.
3Reliability
If the dielectric layer is made thicker to prevent metal migration, then migration resistance improves, but stress concentration increases leading to cracks
Solution Approach 1:
Instead of using a single thick dielectric layer, the barrier is segmented into multiple thinner sub-layers separated by intermediate stress relief layers. Each sub-layer is thin enough to avoid excessive stress concentration, while the cumulative thickness maintains adequate metal migration prevention. The intermediate layers distribute and reduce stress throughout the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces the risk of metal migration and electrical shorts, enhancing the reliability and yield of LED chips by making the dielectric barrier more robust and tolerant to thermal stresses.
Implementation Method 1
the dielectric barrier layer can be used as a barrier layer to prevent migration of metal within the chip
Implementation Method 2
trenches can be formed in or through the dielectric barrier layer to decouple stress in the interior portion of the chip from the portions of the dielectric material at the edge of the chip
Implementation Method 3
the dielectric barrier structure can include a crack reducing interlayer between upper and lower portions of the dielectric barrier layer that precludes or reduces the stress from the die attach metals on the upper dielectric layer from transferring to the lower dielectric barrier layer
Implementation Method 4
stress can be generated in the dielectric barrier layer during heating/cooling due to differences in the thermal coefficients of expansion of various materials in the chip structure
Data Source
AI summary
A light emitting device includes an epitaxial region, an insulating layer on the epitaxial region, a bond pad on the insulating layer, and a crack reducing feature in the insulating layer. The crack reducing feature is configured to reduce the propagation of cracks in the insulating layer to an outside surface of the insulating layer. Related methods are also disclosed.