Light Emitting Device Buffer Region Thermal Stress
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Solution Overview
Problem
The mismatch in thermal expansion coefficients between light emitting chips and carriers leads to thermal stress and warpage issues in light emitting devices, reducing their reliability.
Innovation Solution
A light emitting device design featuring a substrate with an electrode connection layer that includes a buffer region, an insulating layer, and epitaxial structures, which helps to mitigate thermal stress by acting as a buffer between layers with different thermal expansion coefficients, thereby enhancing the device's reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If metal bonding is used to bond the light emitting chip to the carrier at elevated temperatures, then bonding strength is improved, but thermal stress and warpage increase due to thermal expansion coefficient mismatch
Solution Approach 1:
The patent introduces a buffer region as an intermediary layer between the light emitting chip and the carrier. This buffer region acts as a mediator that absorbs and distributes the thermal stress generated during high-temperature bonding, preventing direct transmission of stress to the chip and carrier interfaces, thereby maintaining bonding strength while reducing thermal stress accumulation and warpage
Solution Approach 2:
The patent modifies the structural parameters by introducing a buffer region with specific geometric characteristics (empty gap or low-modulus material) between the chip and carrier. This parameter change allows the system to accommodate thermal expansion differences through the buffer's compliance, reducing thermal stress while maintaining reliable bonding at elevated temperatures
2Adaptability or versatility
If the light emitting chip is disposed on a carrier with molding compound packaging, then application versatility is improved, but thermal stress and warpage increase, reducing reliability
Solution Approach 1:
The buffer region serves as an intermediary structure between the light emitting chip and the carrier package. This intermediary layer absorbs thermal stress generated during packaging and operation, preventing stress transmission that would cause warpage and reliability issues, while still allowing the chip to be mounted on various carrier types for different applications
3Adaptability or versatility
If thermal expansion coefficient mismatch between light emitting chip and carrier is present, then material selection flexibility is maintained, but thermal stress increases, causing warpage and reducing reliability
Solution Approach 1:
The buffer region acts as a stress-absorbing intermediary that decouples the thermal expansion mismatch between the chip and carrier. This allows different materials with varying thermal expansion coefficients to be used in the chip and carrier without direct stress interaction, maintaining material selection flexibility while preventing thermal stress-induced warpage and reliability degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer region in the electrode connection layer effectively reduces thermal stress and improves the reliability of the light emitting device by allowing for better thermal energy transfer and positioning accuracy, leading to a more stable and efficient light emitting performance.
Implementation Method 1
Because of the mismatch of the thermal expansion coefficient of the light emitting chip and the carrier, the thermal stress generated
Implementation Method 2
a light emitting device includes a substrate, an electrode connection layer, and at least one epitaxial structure
Data Source
AI summary
A light emitting device of the invention includes a substrate, an electrode connection layer, and at least one epitaxial structure. The substrate has an upper surface and a plurality of electrode pads disposed on the upper surface. The electrode connection layer is disposed on the upper surface of the substrate and electrically connected to the plurality of electrode pads. The electrode connection layer has at least one first electrode, at least one second electrode and at least one connection layer disposed between the substrate and the at least one first electrode and disposed between the substrate and the at least one second electrode. The at least one connection layer has at least one buffer region exposed on the upper surface of the substrate and being an empty gap. The at least one epitaxial structure is disposed on and electrically connected to the electrode connection layer.