LED Carrier Array Electrical Testing for Yield
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Solution Overview
Problem
In semiconductor manufacturing, the yield rate of subsequent processes is affected when ICs with varying lead frame electrical properties are arbitrarily bonded, leading to inconsistent results.
Innovation Solution
A carrier array with a lead frame and controllers, where second pins are separated and electrically connected through bonding wires or conductive bumps, allowing for electrical testing to grade and select lead frames based on their properties for optimal chip pairing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If lead frames with different electrical properties are arbitrarily bonded to chips, then the manufacturing process can proceed without additional testing steps, but the yield rate of subsequent processes is affected and becomes inconsistent
Solution Approach 1:
The patent applies preliminary action by performing electrical testing on lead frames before they are bonded to chips. The testing is conducted in advance to determine the electrical properties of each lead frame, and only lead frames that meet specified criteria are selected for bonding. This preliminary selection process ensures high yield rates in subsequent manufacturing steps while maintaining manufacturing efficiency.
2Reliability
If electrical testing is performed on all lead frames to ensure proper electrical properties, then the yield rate of subsequent processes is improved, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The patent applies local quality by implementing electrical testing and selection only for lead frames that require verification of specific electrical properties. Not all lead frames undergo the same level of testing - only those where electrical property verification is critical to the final product performance. This selective approach maintains high yield rates while avoiding unnecessary complexity in the overall manufacturing process.
3Reliability
If electrical testing and grading of lead frames is implemented, then the compatibility between lead frames and chips is improved, but the manufacturing time and process steps increase
Solution Approach 1:
The patent performs electrical testing and grading of lead frames as a preliminary step before chip bonding. By determining the electrical properties of lead frames in advance and categorizing them into different grades, the system ensures that only compatible lead frame-chip pairs are bonded together. This preliminary classification prevents time-consuming rework and ensures high electrical compatibility in the final product.
Data Source
AI summary
A carrier array adapted for carrying a plurality of chips is provided. The carrier array includes a lead frame, controllers and first packages. The lead frame includes a frame body and a plurality of lead frame units. The lead frame units are connected with each other through the frame body and arranged in an array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins not connected with the frame body. The controllers are disposed on the lead frame units, and electrically connected with the corresponding lead frame units, respectively. Each of the first packages is disposed on the lead frame, and respectively has an opening to expose a portion region of the corresponding lead frame unit, and the openings are adapted for accommodating the chips. A light emitting diode package is also provided.