Mixed Clock Domain Signaling for LED Cascade Data Integrity
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Solution Overview
Problem
In high-resolution LED displays, the complexity and cost of LED panels increase due to densely populated driver circuit boards, and the challenge of multiple uncorrelated clock domains leads to sampling jitter, causing data integrity issues in cascade communication.
Innovation Solution
Mixed clock domain signaling is implemented, where the bit period is maintained and correlated to the original clock domain throughout cascade communication, using a master controller's clock domain and a local clock domain at each LED package, avoiding the need for separate clock recovery hardware and reducing sampling jitter by retransmitting the original clock domain and synchronizing data segments within the LED package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock recovery hardware is added to each LED package, then sampling jitter can be reduced and data integrity improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the original clock domain signal with data segments in a mixed clock domain signaling protocol, eliminating the need for separate clock recovery hardware at each LED package. The bit start segment carries timing information from the original clock domain, allowing receiving packages to synchronize without dedicated clock recovery circuits.
Solution Approach 2:
The communication channel is designed to serve multiple functions simultaneously: it transmits both data information and clock timing information through the same signal path. The mixed clock domain signal structure allows the data communication channel to also function as a clock distribution channel, reducing overall system complexity.
2Manufacturing precision
If densely populated driver circuit boards are used to achieve high resolution, then pixel pitch decreases and display quality improves, but device complexity and cost increase
Solution Approach 1:
The patent segments the display into multiple LED packages arranged in a cascade topology, where each package contains fewer LED elements. This segmentation allows communication signals to be distributed serially through the cascade chain, reducing the complexity of driver circuit boards compared to parallel driving schemes required for high-density displays.
Solution Approach 2:
The patent introduces a time dimension to the control architecture by using serial cascade communication. Instead of controlling all pixels simultaneously through complex parallel circuits, the system sequentially addresses packages along the cascade chain, trading spatial complexity for temporal sequencing.
3Adaptability or versatility
If multiple uncorrelated clock domains are used in cascade communication, then each LED package can operate independently, but sampling jitter increases and data integrity deteriorates
Solution Approach 1:
The patent introduces a mixed clock domain signaling protocol as an intermediary mechanism that bridges multiple independent clock domains. The bit start segment acts as a mediator carrying timing reference information from the original clock domain through the cascade chain, allowing independently operating packages to maintain synchronization without requiring correlated clock domains.
Data Source
AI summary
Mixed clock domain signaling and, more particularly, mixed clock domain signaling for light-emitting diode (LED) packages arranged for cascade communication is disclosed. Mixed clock domain signaling involves digital communication where time-positions of bit pulse edges in a communication channel are derived from multiple uncorrelated clock domains, including an original clock domain from a master controller and a local clock domain. In the context of LED displays, serial strings of LED packages are arranged as LED pixels to receive cascade communication signals, and the original clock domain is derived from a master controller and a local clock domain is derived at each LED package. By providing for the bit period to be maintained and correlated to the original clock domain throughout the repeated cascade communication, problems associated with multiple uncorrelated clock domains in the communication channel, such as sampling jitter, may be averted, thus avoiding loss of data integrity.