LED Chip Transfer on Auxiliary Carrier for Pixel Alignment
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Solution Overview
Problem
Existing methods for producing lighting devices face challenges in achieving high yield and low costs, often resulting in pixel faults due to crystal lattice defects and image offsets from high tolerance ranges during chip transfer.
Innovation Solution
A method involving the production of optoelectronic semiconductor chips from a wafer assemblage, where the chips are first transferred to an auxiliary carrier, cut to size, and then pixelated before being transferred to a final carrier, allowing for precise adaptation and reduced image offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are transferred directly to the final carrier with high tolerance ranges, then the transfer process is simpler and faster, but image offsets occur reducing manufacturing precision
Solution Approach 1:
The patent introduces an auxiliary carrier as an intermediary component between the chip array and the final carrier. The auxiliary carrier receives the chip array, allows precise cutting to size, and then transfers the pixelated chips to the final carrier. This intermediary step enables precise positioning and reduces image offsets while maintaining efficient production flow.
2Ease of manufacture
If cost-effective singulation methods are used to separate chips, then production costs are reduced, but pixel faults occur due to crystal lattice defects
Solution Approach 1:
The patent performs the cutting to size operation on the auxiliary carrier before transferring the chips to the final carrier. This preliminary action allows the use of cost-effective singulation methods while maintaining pixel quality, as the cutting is done in a controlled environment where the chip array is still supported by the auxiliary carrier, reducing the risk of crystal lattice defects and pixel faults.
3Manufacturing precision
If chips are cut to size before transfer, then precise adaptation to predefined shapes is achieved, but the process complexity increases
Solution Approach 1:
The auxiliary carrier serves as a dedicated workstation for the cutting to size operation. By concentrating the cutting process on this intermediary carrier, the system achieves precise chip adaptation to predefined shapes while managing process complexity through modularization. The auxiliary carrier can be easily replaced or adjusted without affecting the entire production system.
4Ease of operation
If high tolerance ranges are used during chip transfer, then the transfer process is more robust and faster, but image offsets reduce manufacturing precision
Solution Approach 1:
The patent replaces direct mechanical transfer with a two-stage process involving the auxiliary carrier. The auxiliary carrier allows for precise positioning and alignment of the chip array before transfer to the final carrier. This substitution of the direct mechanical transfer system with an intermediary positioning system enables both robustness and high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the yield and reduces costs by allowing precise control over chip size and placement, minimizing pixel faults and image offsets, and enabling the use of cost-effective singulation methods.
Implementation Method 1
The active region serves for generating electromagnetic radiation. The active region includes in particular at least one quantum well structure in the form of a single quantum well, SQW for short, or in the form of a multiquantum well, MQW for short, structure. By way of example, electromagnetic radiation in the blue or green or red spectral range or in the UV range or IR range is generated in the active region during operation as intended.
Implementation Method 2
The dicing method is parallel dicing or a laser-assisted dicing method, for example, in which before the wafer assemblage is diced, a laser is used to introduce defects into the wafer assemblage and thereby predefine target dicing locations, also known by the term stealth dicing.
Implementation Method 3
By way of example, the wafer assemblage is severed by an etching method, such as plasma etching, for example.
Implementation Method 4
By way of example, the semiconductor layer sequence was epitaxially deposited on a growth substrate, for example by means of metal organic vapor phase epitaxy, MOVPE for short, or metal organic chemical vapor deposition, MOCVD for short
Implementation Method 5
By way of example, the semiconductor layer sequence was epitaxially deposited on a growth substrate, for example by means of metal organic vapor phase epitaxy, MOVPE for short, or metal organic chemical vapor deposition, MOCVD for short
Data Source
AI summary
In an embodiment a method for producing a lighting device includes providing a wafer assemblage having a semiconductor layer sequence arranged on a carrier substrate, separating the wafer assemblage into a plurality of first optoelectronic semiconductor chips, each comprising a section of the semiconductor layer sequence and of the carrier substrate, transferring at least some of the first optoelectronic semiconductor chips to a first auxiliary carrier, wherein the first auxiliary carrier has contact pads on a main surface, wherein the contact pads are surrounded and delimited in each case by a contour, and wherein each of the first optoelectronic semiconductor chips is arranged on a contact pad, cutting, on the first auxiliary carrier, to size the first optoelectronic semiconductor chips in order to adapt the first optoelectronic semiconductor chips to a predefined shape such that the each first optoelectronic semiconductor chip lies completely within the contour of an assigned contact pad, and transferring the first optoelectronic semiconductor chips from the first auxiliary carrier to a carrier.