LED Chip Quantum Barrier Doping for Low-Capacitance Displays
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Solution Overview
Problem
Conventional Mini-LED technology in backlight and RGB displays suffers from high capacitance and charge storage capacity, leading to display lag and dimming issues due to high silicon doping concentrations in the quantum barrier layers.
Innovation Solution
The LED chip structure reduces N-type doping concentration in at least two quantum barrier layers of the active layer to no greater than 4E17 atoms/cm3, adjusting capacitance and improving ESD performance through specific layer configurations and materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high silicon doping concentration (≥5E17 atoms/cm3) is used in quantum barrier layers, then ESD performance is improved, but capacitance becomes too high causing display lag and dimming
Solution Approach 1:
The patent applies different doping concentrations to different quantum barrier layers within the active layer. Specifically, at least two quantum barrier layers have N-type doping concentration ≤4E17 atoms/cm3 to reduce capacitance, while other quantum barrier layers maintain higher doping concentrations to ensure ESD performance. This local differentiation resolves the contradiction between low capacitance and high ESD performance.
Solution Approach 2:
The active layer is segmented into multiple quantum barrier layers with different doping characteristics. By dividing the active layer into segments with varying doping concentrations, the patent achieves both low overall capacitance (through low-doped layers) and adequate ESD performance (through high-doped layers), preventing display lag and dimming issues.
2Power
If high silicon doping concentration is used in quantum barrier layers, then voltage is reduced, but charge storage capacity becomes too strong affecting backlight and RGB display performance
Solution Approach 1:
Different quantum barrier layers are assigned different doping concentrations to balance voltage and charge storage. Layers with ≤4E17 atoms/cm3 doping provide lower charge storage capacity suitable for display applications, while maintaining adequate voltage through the overall structure design and other higher-doped layers.
Data Source
AI summary
An LED chip structure and a display device are disclosed in the disclosure. The LED chip structure includes a semiconductor stack layer. The semiconductor stack layer includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer. The active layer is disposed above the P-type semiconductor layer. The active layer includes multiple layers formed by repeatedly stacking a well layer and a quantum barrier layer. The P-type semiconductor layer is disposed above the active layer. The N-type peak doping concentration of at least two quantum barrier layers of the active layer is no greater than 4E17 atoms/cm3.


