LED Chip Graphical Current Extension Layers
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Solution Overview
Problem
Existing light emitting diode (LED) chip production technologies face issues with low brightness due to defects caused by crystal mismatch and reduced light emitting areas, as well as adhesion problems with wire bonding pads, leading to lower reliability and utilization of medium and small-sized chips.
Innovation Solution
A light emitting diode chip structure is developed with a rectangular substrate, featuring N-type and P-type semiconductor layers, graphical current extension layers, electrical-insulating layers, and reflectors, which increase the light emitting area and adhesion of pads, improving current distribution and brightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the chip size is reduced to medium and small sizes, then the manufacturing cost is reduced and utilization is improved, but the light emitting area is reduced and brightness is lowered
Solution Approach 1:
The patent extends the current path from a two-dimensional surface pattern into the third dimension by creating vertical current extension layers that penetrate through the semiconductor layers. This allows current to flow through additional vertical pathways, effectively increasing the active current-carrying area without expanding the chip's planar footprint, thus maintaining brightness in smaller chips.
Solution Approach 2:
The current extension layer is divided into multiple graphical patterns (such as mesh, grid, or dotted structures) that segment the current flow into multiple parallel pathways. This segmentation increases the total effective current-carrying area within the confined chip size, allowing more current to be distributed across the light emitting region without requiring a larger chip area.
2Reliability
If the pad size is increased to improve adhesion, then the bonding reliability is improved, but the light emitting area is further reduced
Solution Approach 1:
The patent addresses pad adhesion by extending current pathways vertically through the semiconductor layers rather than relying solely on increasing pad surface area. The current extension layers provide additional vertical bonding interfaces that enhance mechanical adhesion and electrical connection without requiring larger horizontal pad dimensions, thus preserving light emitting area.
3Ease of manufacture
If conventional wire bonding pads are used on a flat surface, then the manufacturing process is simple, but the adhesion is poor and the chip pulls off the pad under thermal stress
Solution Approach 1:
The patent transitions from a two-dimensional flat pad structure to a three-dimensional vertical current extension structure. The current extension layers create multiple vertical bonding interfaces within the semiconductor stack, providing enhanced mechanical interlocking and thermal stress distribution without complicating the overall manufacturing process flow.
Solution Approach 2:
The patent employs composite structures by integrating current extension layers made of different semiconductor materials with varying properties into the chip stack. These composite layers provide both electrical conductivity and enhanced mechanical adhesion, creating a multi-functional structure that simultaneously improves bonding reliability and maintains manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances light emitting brightness and adhesion of pads, increasing the reliability of LED chips by optimizing current distribution and pad adhesion without affecting semiconductor layer performance.
Implementation Method 1
the back of the P pad and the back of the N pad are respectively provided with reflectors
Data Source
AI summary
A semiconductor light emitting diode chip relates to the field of production technologies of a light emitting diode. In the present invention, corresponding graphical current extension layers are respectively disposed below an N pad and a P pad, and in all light emitting compound areas, there is electronic compound light emitting. Compared with the prior art, an area of a light emitting compound area is increased, which can effectively improve current distribution and light emitting brightness of a chip. In addition, graphical current extension can effectively increase an adhesion of a pad on a surface and improve the reliability of a chip.