LED Chip Fabrication via Integrated Current Blocking and Passivation
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Solution Overview
Problem
The conventional method of fabricating light emitting diode (LED) chips requires multiple photolithography and etching processes, leading to high costs and prolonged fabrication time due to the need for multiple masks and complex steps.
Innovation Solution
A method that simplifies the fabrication process by forming the current blocking layer and passivation layer simultaneously using a dielectric layer, reducing the number of steps and masks required, and utilizing a patterned functional layer with multi-layer structures to improve alignment accuracy and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography and etching processes are used to form current blocking layer and passivation layer separately, then the fabrication precision and reliability are improved, but the fabrication cost and time increase
Solution Approach 1:
The patent combines the formation of current blocking layer and passivation layer into a single photolithography and etching process by using a patterned functional layer with both layers integrated. This merging approach reduces the number of separate fabrication steps while maintaining the precision of individual layer formation, thereby reducing fabrication time and cost without sacrificing manufacturing precision.
2Manufacturing precision
If multiple masks are used for separate formation of current blocking layer and passivation layer, then the manufacturing precision is improved, but the device complexity and cost increase
Solution Approach 1:
The patent merges the formation of current blocking layer and passivation layer into a single process step using a patterned functional layer that contains both layers. This eliminates the need for multiple separate masks and photolithography steps, reducing process complexity and mask costs while maintaining alignment accuracy through the integrated design of the patterned functional layer.
Solution Approach 2:
The patterned functional layer serves multiple functions simultaneously: it acts as both the current blocking layer and the passivation layer, and also provides structural support and electrical isolation. This multi-functionality reduces the overall number of components and process steps required, simplifying the fabrication process while maintaining manufacturing precision.
3Reliability
If conventional separate formation process is used for current blocking layer and passivation layer, then the reliability is improved, but the fabrication cost increases
Solution Approach 1:
The patent combines the formation of current blocking layer and passivation layer into a single integrated process using a patterned functional layer. This reduces the number of fabrication steps, masks, and materials required, thereby lowering fabrication costs while maintaining chip reliability through the preserved functional integrity of both layers.
Solution Approach 2:
The patterned functional layer is formed as a composite structure containing both the current blocking layer and passivation layer in a single integrated component. This composite approach maintains the distinct functional properties of each layer while reducing overall manufacturing complexity and cost, as the layers are formed simultaneously in one process step rather than separately.
Data Source
AI summary
A method for fabricating a light emitting diode chip is provided. Firstly, a semiconductor device layer is formed on a substrate. Afterwards, a current spreading layer is formed on a portion of the semiconductor device layer. Then, a current blocking layer and a passivation layer are formed on a portion of the semiconductor device layer not covered by the current spreading layer. Finally, a first electrode is formed on the current blocking layer and the current spreading layer. Moreover, a second electrode is formed on the semiconductor device layer.