LED Chip Structures with Reduced Bonding Topography
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Solution Overview
Problem
The efficiency of light extraction and quantum efficiency in LEDs is limited by internal reflection and current spreading issues, particularly in larger area LEDs, which hinders the development of improved solid-state lighting devices.
Innovation Solution
The introduction of reduced bonding topography between active LED structures and carrier submounts, along with specific electrical connection configurations and peripheral border configurations, enhances bonding strength and light extraction, utilizing metal bonding techniques and reflective structures to improve current spreading and light transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional bonding techniques are used between active LED structures and carrier submounts, then bonding can be achieved, but bonding strength is insufficient due to bonding topography
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer over the active LED structure before bonding to the carrier submount. This planarization layer pre-compensates for the bonding topography, creating a flat bonding surface that ensures strong and uniform bonding between the LED structure and carrier submount.
Solution Approach 2:
The patent introduces a planarization layer as an intermediary between the active LED structure and the carrier submount. This intermediate layer fills in the bonding topography and provides a uniform bonding interface, thereby improving bonding strength while accommodating the underlying structural variations.
2Illumination intensity
If light extraction is maximized, then emission efficiency improves, but internal reflection reduces the amount of light that can exit the LED
Solution Approach 1:
The patent applies curvature by forming a domed encapsulant over the active LED structure. This domed shape creates a curved interface that reduces total internal reflection at the LED-encapsulant boundary, allowing more light to escape and improving light extraction efficiency while minimizing energy loss to internal reflection.
3Reliability
If current spreading is increased in larger area LEDs, then quantum efficiency improves, but additional layers and electrode extensions increase device complexity
Solution Approach 1:
The patent merges multiple functions into the electrode structure by integrating current spreading layers with the electrode pattern. The electrode extensions serve dual purposes: providing electrical connection and facilitating current spreading across the active region, thereby improving quantum efficiency without proportionally increasing device complexity.
Solution Approach 2:
The patent applies multi-functionality by designing electrode structures that simultaneously provide electrical connection, current spreading, and mechanical support. The electrode extensions are configured to route current while also acting as current spreading elements, allowing a single structural feature to fulfill multiple functional requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the bonding strength and light extraction efficiency of LEDs, leading to enhanced illumination characteristics and overcoming challenges associated with conventional lighting devices.
Implementation Method 1
When a bias is applied across the doped layers, holes and electrons are injected into the one or more active layers where they recombine to generate emissions such as visible light or ultraviolet emissions
Implementation Method 2
Reflective surfaces may also be provided to reflect generated light so that such light may contribute to useful emission from an LED chip
Data Source
AI summary
Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.