LED Clock Generating Circuit Reducing Power via Periodic Delay Cell Adjustment
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Solution Overview
Problem
Conventional LED driving devices consume excessive power due to continuous adjustment of delay cells by phase detectors, which is inefficient in power management.
Innovation Solution
A clock generating circuit that adjusts delay cells only when necessary, using a controller to generate window signals and count pulses to set delay times within a predetermined range, selectively driving required circuits to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase detector and multi-stage delay chain are used to continuously adjust delay cells for generating GCLK, then the clock generation accuracy is improved, but power consumption increases significantly
Solution Approach 1:
The patent applies periodic action by using window signals to enable delay cells only during specific time periods (first time period for even-numbered pulses, second time period for odd-numbered pulses) instead of continuous operation. This periodic enabling reduces power consumption while maintaining clock generation accuracy through timed adjustments.
Solution Approach 2:
The patent segments the delay cell operation into distinct groups: even-numbered delay cells are adjusted during the first time period, while odd-numbered delay cells are adjusted during the second time period. This segmentation allows different subsets of delay cells to be activated at different times, reducing overall power consumption while maintaining accuracy.
2Adaptability or versatility
If multiple delay cells are driven continuously by up-down signals from a phase detector, then the adaptability of clock frequency adjustment is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by alternating between two time periods: the first time period for adjusting even-numbered delay cells and the second time period for adjusting odd-numbered delay cells. This periodic operation maintains frequency adaptability while significantly reducing power consumption compared to continuous operation of all delay cells.
Solution Approach 2:
The patent applies dynamics by making the delay cell operation dynamic rather than static - delay cells are selectively enabled and disabled based on the current time period and adjustment needs. This dynamic operation allows the system to maintain adaptability while optimizing power consumption by activating only the necessary delay cells at any given time.
3Reliability
If all delay cells are kept active for continuous monitoring and adjustment, then the reliability of clock generation is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic action to maintain reliability by systematically alternating between adjusting even-numbered and odd-numbered delay cells in different time periods. This ensures that all delay cells remain functional and monitored over time while reducing instantaneous power consumption, as not all cells need to be fully active simultaneously.
Data Source
AI summary
The present disclosure provides a technique for reducing power consumption of circuits generating clocks for driving LEDs.