LED Dimming Circuit Signal Processing Method
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Solution Overview
Problem
The integration of high resistance and capacitance RC filters for LED dimming is challenging due to size constraints and low response rates, making it difficult to achieve effective dimming control with low dimming frequencies.
Innovation Solution
A signal processing circuit that determines high and low level sampling pulse amounts from a PWM signal and generates a new PWM signal with a higher frequency, maintaining the same duty cycle, which reduces the need for large RC filters and improves integration and response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high resistance and capacitance RC filters are used for LED dimming, then dimming control performance is improved, but circuit integration is difficult and response rate is low
Solution Approach 1:
The patent replaces the traditional RC filter-based dimming control mechanism with a PWM signal processing mechanism. Instead of using physical RC circuits to convert PWM duty cycle to linear voltage signals, the invention uses digital signal processing to count PWM high-level pulses and generate corresponding sampling pulse signals, thereby substituting analog filtering with digital counting and signal generation.
Solution Approach 2:
The patent changes the fundamental parameter representation from analog voltage levels (produced by RC filters) to digital pulse counts. By counting the number of PWM high-level pulses within a period and generating an equivalent number of sampling pulses, the system transforms the dimming control from continuous analog adjustment to discrete digital pulse modulation, improving integration and response speed.
2Reliability
If high resistance and capacitance RC filters are used for LED dimming, then dimming control performance is improved, but response rate is low
Solution Approach 1:
The patent replaces the traditional RC filter-based dimming control mechanism with a PWM signal processing mechanism. Instead of using physical RC circuits to convert PWM duty cycle to linear voltage signals, the invention uses digital signal processing to count PWM high-level pulses and generate corresponding sampling pulse signals, thereby substituting analog filtering with digital counting and signal generation.
Solution Approach 2:
The patent ensures continuous and immediate response by generating sampling pulse signals that directly follow the PWM signal cycles without the delay inherent in RC filter charging and discharging. The sampling circuit continuously counts PWM pulses and generates corresponding output pulses in real-time, eliminating the transient response delays characteristic of analog filtering circuits.
3Reliability
If traditional RC filter method is used, then dimming performance is maintained, but large resistors and capacitors are required
Solution Approach 1:
The patent replaces the traditional RC filter-based dimming control mechanism with a PWM signal processing mechanism. Instead of using physical RC circuits to convert PWM duty cycle to linear voltage signals, the invention uses digital signal processing to count PWM high-level pulses and generate corresponding sampling pulse signals, thereby substituting analog filtering with digital counting and signal generation.
Solution Approach 2:
The patent changes the fundamental parameter representation from analog voltage levels (produced by RC filters) to digital pulse counts. By counting the number of PWM high-level pulses within a period and generating an equivalent number of sampling pulses, the system transforms the dimming control from continuous analog adjustment to discrete digital pulse modulation, improving integration and response speed.
Data Source
AI summary
In one embodiment, method of signal processing can include: (i) determining a high level sampling pulse amount by counting a number of pulses of a first clock signal during a high level portion of a period of a first PWM; (ii) generating a first pulse signal based on a second clock signal and the high level sampling pulse amount; (iii) determining a low level sampling pulse amount by counting a number of pulses of the first clock signal during a low level portion of the period of the first PWM signal; (iv) generating a second pulse signal based on the second clock signal and the low level sampling pulse amount; and (v) generating a second PWM signal based on the first and second pulse signals.


