LED Driver Circuit Using Delay-Locked Loop for Area Reduction
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Solution Overview
Problem
Conventional LED driver chips require significant human resources and time to design due to their complex circuit architectures and the need for separate designs for common-anode and common-cathode configurations, and the phase-locked loop (PLL) used in LED driver chips occupies a large area and is difficult to adjust with semiconductor process changes.
Innovation Solution
A display system with a driving circuit that includes a delay-locked loop (DLL), a signal processor, a scan driver, and a channel driver, which generates internal global clock signals and provides control outputs for scan and channel lines, allowing for efficient driving of light emitting arrays with either common cathode or common anode configurations, reducing the need for extensive redesign and minimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) is used to generate a global clock signal in an LED driver chip, then the clock signal can be generated, but the circuit occupies a large area and requires dramatic adjustments in circuit parameters and architecture when the semiconductor process changes
Solution Approach 1:
The patent replaces the traditional analog PLL circuit with a digital delay-locked loop (DPLL) circuit. The DPLL uses digital logic elements (D flip-flops, multiplexers, and delay elements) instead of analog components to generate the global clock signal. This substitution reduces the circuit area significantly and makes the design more adaptable to different semiconductor processes, as digital circuits are generally more process-insensitive than analog circuits.
2Adaptability or versatility
If separate circuit architectures are designed for common-anode and common-cathode LED driver chips, then each configuration can be optimized, but significant human resources and time are consumed in the design process
Solution Approach 1:
The patent designs a universal LED driver chip architecture that can support both common-anode and common-cathode LED array configurations. The circuit includes configurable elements such as selectable current mirror arrangements and adaptable scan/channel line connections that can be programmed or switched to match different LED configurations. This universal design eliminates the need for separate dedicated designs for each configuration type, significantly reducing development time and resources while maintaining optimization capabilities for both configurations.
Data Source
AI summary
A display system includes a light emitting array and a driving circuit. The light emitting array includes: a plurality of scan lines, a plurality of channel lines, and a plurality of light emitting elements connected to the scan lines and the channel lines. The driving circuit includes: a delay-locked loop generating an internal global clock signal; a signal processor generating a scan control output and a channel control output based on the internal global clock signal and display data; a scan driver driving the scan lines based on the scan control output; and a channel driver providing a plurality of driving current signals respectively to the channel lines based on the channel control signal.