LED Driver Gate Clamp Circuit for PWM Current Spike Reduction

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Solution Overview

Problem

In electronic devices with LED displays, pulse-width-modulation (PWM) control of LEDs can lead to current spikes due to the operational amplifier's feedback loop issues during the off pulses of the PWM transistor, causing voltage spikes at the rising edge of the PWM cycle, which can result in electromagnetic interference and reduced reliability of the LED driver circuitry.

Innovation Solution

A gate clamp circuit is introduced to clamp the gate voltage of the current regulation transistor to a voltage at or slightly above the regulating voltage during the on pulse of the PWM cycle, allowing the gate voltage to be quickly returned to the regulation value when the feedback loop is reconnected, thereby reducing or eliminating current spikes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If pulse-width-modulation control is used to control LED current, then LED brightness control is achieved, but current spikes and voltage spikes occur at the rising edge of PWM cycle

Engineering Contradiction:
ImproveLED brightness controlVSAvoidLED driver circuitry reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The gate clamp circuit is activated before the PWM rising edge to pre-clamp the current regulation transistor gate voltage. This preliminary action ensures that when the PWM signal transitions high, the gate voltage is already constrained, preventing the feedback loop from causing voltage spikes and current spikes. The clamp circuit prepares the circuit state in advance to avoid the harmful effects during the critical transition period.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If feedback loop is used for current regulation, then current control accuracy is improved, but voltage spikes occur at PWM rising edge due to loop response delay

Engineering Contradiction:
Improvecurrent control accuracyVSAvoidvoltage spikes
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The gate clamp circuit applies a counteracting constraint on the gate voltage before the PWM rising edge occurs. By clamping the gate voltage to a maximum level (VDD - Vth) in advance, the circuit prevents the feedback loop's delayed response from causing voltage spikes. This preliminary anti-action neutralizes the potential harmful effect before it can manifest, allowing the feedback loop to maintain accuracy without generating spikes.

Inventive Principle:
Principle #9Preliminary anti-action

3Speed

If gate voltage is allowed to rise quickly during PWM on pulse, then current response speed is improved, but electromagnetic interference is generated

Engineering Contradiction:
Improvecurrent response speedVSAvoidelectromagnetic interference
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The gate clamp circuit is enabled before the PWM rising edge to pre-establish the gate voltage clamping condition. This preliminary action ensures that when the PWM signal goes high, the gate voltage can rise quickly to the clamped level without overshooting or creating EMI. The clamp circuit is already in place to guide the voltage transition smoothly, achieving fast response without electromagnetic interference.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20180332678A1LED driver gate clamp systems and methods
Publication Date: 2018.11.15 APPLE INC
  • US20180332678A1 patent drawing
  • US20180332678A1 patent drawing
  • US20180332678A1 patent drawing

AI summary

Aspects of the subject technology relate to display circuitry such as backlight control circuitry for operating light-emitting diodes (LEDs). The backlight control circuitry may include a pulse-width-modulation (PWM) transistor and a current regulation transistor coupled in series with at least one LED. The current regulation transistor may have a gate terminal that receives a feedback-controlled gate voltage. The backlight control circuitry may include a gate clamp circuit coupled to the gate terminal of the current regulation transistor that clamps the gate voltage during a portion of a PWM on pulse.