LED Package Encapsulation Layers for Delamination Resistance

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Solution Overview

Problem

Conventional LED packages face internal stress issues due to curing and operational conditions, leading to delamination of LED chips and encapsulation material, which can result in catastrophic failure and performance degradation.

Innovation Solution

The implementation of a multi-layer encapsulation structure where a first encapsulation layer covers the recess floor and sidewalls of the LED chips, with a second encapsulation layer covering the first layer, allowing the first layer to buffer internal stresses and mitigate delamination risks, and the weight percentage of the first encapsulation layer is optimized to be less than 50% of the total encapsulation weight, typically ranging from 3% to 10%.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-layer encapsulation structure is used, then the device complexity is reduced, but internal stresses during operation cause delamination of LED chips

Engineering Contradiction:
Improveencapsulation structure complexityVSAvoiddelamination resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The encapsulation structure is divided into multiple layers: a first encapsulation layer applied to the recess floor and LED chip sidewalls, and a second encapsulation layer applied over the first layer. This segmentation allows each layer to perform specific stress-buffering functions, preventing delamination while maintaining structural integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first encapsulation layer is applied beforehand to the recess floor and LED chip sidewalls to create a stress-absorbing buffer before the second encapsulation layer is applied. This prior cushioning prevents internal stresses from directly causing delamination during subsequent curing and operation.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If the first encapsulation layer covers more surface area, then stress buffering capacity increases, but the weight percentage exceeds 50% of total encapsulation weight

Engineering Contradiction:
Improvestress buffering capacityVSAvoidfirst encapsulation layer weight
Core Design Contradiction:
ReliabilityVSWeight of stationary object

Solution Approach 1:

The first encapsulation layer is selectively applied to specific locations where stress concentration occurs - namely the recess floor and LED chip sidewalls - rather than uniformly covering all surfaces. This localized application provides maximum stress buffering capacity while minimizing the weight percentage to below 50% of total encapsulation weight.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The first encapsulation layer is applied to critical stress zones rather than the entire surface, providing sufficient stress buffering capacity through partial coverage. This partial action achieves the necessary reliability without excessive material usage, keeping the weight percentage within acceptable limits.

Inventive Principle:
Principle #16Partial or excessive action

3Ease of manufacture

If conventional encapsulation is used, then manufacturing is simpler, but internal stresses lead to catastrophic failure

Engineering Contradiction:
Improveencapsulation process simplicityVSAvoidcatastrophic failure resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The encapsulation process is segmented into two distinct application steps: first applying the first encapsulation layer to the recess floor and LED chip sidewalls, then applying the second encapsulation layer over it. This segmentation maintains ease of manufacture through straightforward sequential processes while dramatically improving resistance to catastrophic failure by distributing internal stresses across multiple layers.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20230282786A1Encapsulation arrangements in light-emitting diode packages
Publication Date: 2023.09.07 CREELED INC
  • US20230282786A1 patent drawing
  • US20230282786A1 patent drawing
  • US20230282786A1 patent drawing

AI summary

Light-emitting diode (LED) packages and more particularly encapsulation arrangements in LED packages that provide reduced internal stresses are disclosed. LED packages may include housings that form a recess with one or more LED chips provided within the recess. Encapsulation arrangements include multiple encapsulation layers where a first encapsulation layer covers portions of a recess floor and sidewalls of the one or more LED chips, and a second encapsulation layer that covers the first encapsulation layer. In this manner, the first encapsulation layer is configured to buffer internal encapsulation stresses during operation that could lead to delamination of the LED chips.