LED Flicker Suppression via Decision Point Delay Circuit
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Solution Overview
Problem
PWM dimming in LED drivers can cause flicker due to indeterminate conditions resulting from the interaction of duty cycle limits and slope compensation, leading to inconsistent LED current control and potential power droops.
Innovation Solution
A Decision Point (DP) circuit is introduced, which includes a latch that can be in one of two states: coinciding with or delayed relative to the trailing edge of the PWM pulse, and a trigger circuit that adjusts the gate signal to prevent flicker by terminating the duty cycle limit past a decision point, ensuring the inductor current meets the reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PWM dimming is used to control LED brightness, then brightness control range is improved, but flicker occurs due to indeterminate conditions from duty cycle limits and slope compensation interaction
Solution Approach 1:
The patent applies preliminary action by setting a predetermined delay time (first delay time) between the trailing edge of the PWM signal and the decision point for terminating the gate signal. This pre-planned timing arrangement ensures that the inductor current has sufficient time to reach the reference voltage before the gate signal terminates, preventing the indeterminate conditions that cause flicker while maintaining the full PWM dimming control range.
2Speed
If duty cycle limit is enforced in LED driver gate signal, then switching frequency control is improved, but intermittent reset pulses occur causing flicker
Solution Approach 1:
The patent introduces an intermediary delay mechanism between the PWM trailing edge and the gate signal termination decision point. This intermediary delay time acts as a buffer that mediates between the duty cycle limit requirement and the inductor current ramp-up requirement, ensuring that the gate signal terminates only after the current has reached the reference voltage, thereby eliminating intermittent reset pulses while maintaining switching frequency control.
3Reliability
If gate signal terminates at duty cycle limit, then maximum duty cycle protection is improved, but inductor current may not meet reference voltage causing power droop
Solution Approach 1:
The patent applies preliminary action by establishing a predetermined delay time that ensures the inductor current reaches the reference voltage before the gate signal terminates at the duty cycle limit. This pre-planned timing arrangement guarantees that maximum duty cycle protection is maintained while preventing input power droop, as the current has sufficient time to reach the required reference level before the switching cycle ends.
Data Source
AI summary
A circuit for flicker suppression in a Light Emitting Diode (LED) has a latch. The latch has a first state set with a trailing edge of Pulse Width Modulated Dimming (PWMD) pulse, and a second state set delayed with respect to the PWMD trailing edge. A trigger circuit is coupled to the latch. The trigger circuit sends a signal to the latch to change to the second state when a decision point occurs during a time following a duty limit Dmax of a gate of a LED driver circuit.