LED Image Data Layout for Burst Reading From Off-Chip Memory

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Solution Overview

Problem

The efficiency of reading image data from off-chip memory in small-pitch LED display screens is low, limiting the number of data arrays and resolution due to the low efficiency of burst read operations, which is exacerbated by the limitations of on-chip memory resources and the need to maintain uninterrupted data transmission, leading to increased costs and restrictions.

Innovation Solution

An image data reading method that stores image data in v storage blocks, each storing h rows, and reads and outputs the data in a vertical order in a burst mode, utilizing on-chip and off-chip memory to improve data transfer efficiency without altering hardware clock frequencies or bit widths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If image data is read sequentially from off-chip memory using traditional methods, then data transmission continuity is maintained, but reading efficiency is too low and burst read is impossible

Engineering Contradiction:
Improveimage data reading efficiencyVSAvoiddata transmission continuity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the off-chip memory into multiple banks (first bank, second bank, etc.) and stores different image blocks in different banks. This segmentation allows parallel reading operations to occur simultaneously across multiple banks, dramatically improving reading efficiency while maintaining data transmission continuity through coordinated bank switching.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent pre-organizes image data into specific storage patterns before reading operations begin. Image blocks are预先 stored in a manner that enables efficient parallel access - with related image blocks positioned in different banks, allowing the system to perform burst reads by simultaneously accessing multiple banks without interrupting data transmission.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If read-write clock frequency or bit width of external memory is increased to ensure uninterrupted data transmission, then data transmission reliability is improved, but cost increases and hardware restrictions are imposed

Engineering Contradiction:
Improvedata transmission continuityVSAvoidhardware cost and restrictions
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of increasing clock frequency or bit width, the patent segments memory access across multiple banks, achieving parallel data transmission. This approach maintains data transmission reliability through coordinated access to multiple memory banks simultaneously, without requiring higher clock frequencies or wider bit widths, thereby avoiding increased hardware cost and complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimension sequential access model to a multi-dimension parallel access model by utilizing multiple memory banks. This dimensional change allows simultaneous data retrieval from different banks, achieving high-speed uninterrupted transmission without increasing the complexity of individual memory interfaces.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Speed

If on-chip memory resources are used to store image data, then data access speed is improved, but memory resource limitations prevent sufficient storage capacity

Engineering Contradiction:
Improvedata access speedVSAvoidstorage capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent introduces off-chip memory banks as an intermediary storage layer between the processor and the actual image data sources. These banks provide high-speed access comparable to on-chip memory while offering vastly expanded storage capacity, effectively bridging the gap between speed and capacity requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a nested memory architecture where multiple memory banks are organized in a hierarchical structure. Image data is distributed across nested banks, allowing the system to access data at different levels of the hierarchy - with frequently accessed data in faster banks and less frequently accessed data in slower banks, optimizing both speed and capacity utilization.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentEP3734582B1Image data reading method and apparatus, electronic device, and readable storage medium
Publication Date: 2025.11.19 ZHEJIANG UNIVIEW TECH CO LTD
  • EP3734582B1 patent drawingFigure 1
  • EP3734582B1 patent drawingFigure 2
  • EP3734582B1 patent drawingFigure 3~4

AI summary

Disclosed are an image data reading method and apparatus, an electronic device, and a readable storage medium, relating to the technical field of LED image display. The image data reading method includes: storing image data in each row of image blocks into a number of v storage blocks, where each of the v storage blocks stores a number of h rows, each row of data including image data stored at a same position of each group in a same row of every image block; and sequentially outputting from each of the v storage blocks by: sequentially reading each row of the image data in a vertical order, and simultaneously outputting the image data stored at the same position. Without changing the hardware read/write clock frequency or increasing the bit width, the time required for reading image data in an off-chip memory by an LED driver chip is shortened by adopting the burst reading mode.