Light Emitting Device Package Wiring Layout for Chip Arrangement Freedom
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing light-emitting device packages face limitations in wire length during the wire-bonding process and restricted freedom in arranging light-emitting chips due to the geometry of the wiring patterns, which hampers efficient electrical connection and series/parallel connections among the chips.
Innovation Solution
The light-emitting device package features a substrate with first and second wiring layers having concave portions and extension patterns that are symmetrically arranged around a reference line, allowing for flexible positioning of light-emitting chips and facilitating wire bonding by optimizing the distance and alignment between the wiring layers and the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional wiring patterns are used in light-emitting device packages, then the structure is simple, but the freedom in arranging light-emitting chips is restricted and wire length is limited
Solution Approach 1:
The wiring layer is divided into multiple independent wiring patterns, each capable of connecting to different regions of the chip-mounting region. This segmentation allows light-emitting chips to be arranged flexibly without being constrained by a single continuous wiring path, thereby increasing arrangement freedom while maintaining structural simplicity.
Solution Approach 2:
The wiring patterns extend in multiple directions (first direction, second direction, third direction) rather than following a single linear path. This multi-dimensional arrangement allows wires to reach chips positioned at various locations on the substrate, significantly improving arrangement freedom without proportionally increasing overall wiring complexity.
2Adaptability or versatility
If wiring patterns are extended to accommodate flexible chip arrangement, then arrangement freedom improves, but wire bonding complexity and manufacturing difficulty increase
Solution Approach 1:
Different wiring patterns are designed with different extension directions and lengths according to the specific requirements of various chip positions. Each wiring pattern is optimized locally for its intended function, allowing flexible chip arrangement while keeping each individual wire bonding operation relatively simple and manageable.
Solution Approach 2:
The wiring patterns are pre-configured on the substrate before chip mounting, with extension directions and lengths predetermined to accommodate various chip arrangements. This preliminary configuration simplifies the subsequent wire bonding process by providing ready-made connection paths, reducing manufacturing complexity despite the flexibility offered.
3Length of moving object
If multiple wiring patterns with different extension directions are used, then wire length limitations are mitigated, but the device structure becomes more complex
Solution Approach 1:
The wiring patterns are designed to extend dynamically in multiple directions (first, second, and third directions) from different regions of the chip-mounting area. This dynamic multi-directional extension allows the wiring structure to adapt to chips positioned at various distances and locations, effectively increasing the usable wire length without creating a uniformly complex structure throughout.
Solution Approach 2:
The wiring patterns vary in their extension directions, lengths, and starting positions as design parameters. By changing these parameters according to specific connection needs, the system achieves longer effective wire lengths for reaching distant chips while maintaining overall structural simplicity through standardized pattern design rules.
Data Source
AI summary
An embodiment comprises: a substrate having a chip mounting region; first and second wiring layers disposed on the substrate around the chip mounting region so as to be spaced apart from each other; and a plurality of light emitting chips disposed on the chip mounting region, wherein the first wiring layer comprises a first wiring pattern disposed at one side of a reference line and having a first concave part, and a first extending pattern extending from the first wiring pattern to the other side of the reference line, the second wiring layer comprises a second wiring pattern disposed at the other side of the reference line and having a second concave part, and a second extending pattern extending from the second wiring pattern to one side of the reference line, and the reference line is a straight line passing through the center of the chip mounting region.