LED Pixel Circuit Board Layout for Parallel Pre-Packaging Testing
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Solution Overview
Problem
Conventional LED pixel packaging and testing methods are inefficient due to the small size and high quantity of LED packages, making testing difficult and time-consuming, and often result in costly waste if defects are found after sealing, especially when integrated circuit chips are involved.
Innovation Solution
An LED circuit board structure and testing method that includes a carrier board with patterned regions for mounting LEDs and integrated circuit chips, along with testing wires and connecting wires that allow for parallel connection and direct electrical testing before packaging, enabling efficient testing and reducing waste by identifying defects early.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LED pixel packages are tested one by one after sealing, then testing can be performed, but testing becomes time-consuming and inefficient due to small size and large quantity
Solution Approach 1:
The patent segments the testing process by providing separate testing wire sets for different color LEDs (red, green, blue) and different types of LEDs (first and second color LEDs). Each testing wire set is independently configurable to test specific LED types, allowing parallel testing operations and eliminating the need to test all LEDs sequentially one by one.
Solution Approach 2:
The patent implements preliminary action by allowing testing to be performed before the LED pixel packages are sealed into final packages. The testing wires are exposed and accessible on the circuit board before packaging, enabling early detection of defective LEDs. This preliminary testing prevents defective units from being sealed, avoiding waste of packaging materials and reducing rework.
2Reliability
If LED pixel packages are tested after sealing, then testing can be performed, but the entire package must be discarded if a defect is found, resulting in cost waste
Solution Approach 1:
The patent performs testing before the LED pixel packages are sealed into final packages. The testing wires are accessible on the circuit board prior to packaging, allowing defective LEDs to be identified and replaced early in the manufacturing process. This prevents defective units from consuming packaging materials and reduces the need to discard entire packaged units when defects are found.
Solution Approach 2:
The patent extracts the testing function from the final packaged product by providing accessible testing wire sets on the circuit board before packaging. This allows testing to be performed on individual LEDs or LED groups independently, enabling selective replacement of only defective components rather than discarding entire packaged units.
3Adaptability or versatility
If integrated circuit chips are disposed in LED pixel packages for driving LEDs, then functionality is improved, but testing becomes more difficult after packaging
Solution Approach 1:
The patent segments the testing function by providing separate testing wire sets for different LED types (first color LEDs, second color LEDs, and different colors) that are independent of the integrated circuit chip connections. This allows direct testing of LED functionality through the testing wires without needing to activate or depend on the integrated circuit chip driving logic, simplifying the testing process.
Solution Approach 2:
The patent introduces testing wire sets as intermediary elements that provide direct electrical access to LED terminals independent of the integrated circuit chip. These testing wires serve as mediators that allow external testing equipment to directly test LED functionality without needing to interface with or activate the integrated circuit chip driving circuits.
Data Source
AI summary
An LED circuit board structure includes first color LEDs, second color LEDs, third color LEDs, integrated circuit chips, a carrier board, first P-type pads, first color pads, first testing wires and first connecting wires. One of the first P-type pads is disposed at a pixel-front-side-pattern region for mounting a first P-type electrode. One of the first color pads is disposed at the pixel-front-side-pattern region for mounting a first pin of the integrated circuit chip. The first color pad electrically connects to the first P-type pad. A first testing wire is disposed at the pixel-front-side-pattern region and extends from the first P-type pad or the first color pad. The first connecting wire electrically connects two first testing wires in adjacent two pixel-front-side-pattern regions in parallel.