Semiconductor LED Reflective Via Layout for Light Extraction
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Solution Overview
Problem
Conventional semiconductor light-emitting diodes (LEDs) face challenges in light extraction efficiency due to the removal of a substantial portion of the active layer for electrode formation, which reduces the surface area available for light emission and heat dissipation.
Innovation Solution
The semiconductor light-emitting device incorporates a semiconductor stack with depressions that expose the second semiconductor layer, allowing for the formation of contact structures and pad portions on the first surface while maintaining a patterned metal layer that covers the periphery surface, enhancing light extraction and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a substantial portion of the active layer is removed for electrode formation, then the n-type electrode can be formed for wire bonding, but the light extraction efficiency is lowered
Solution Approach 1:
The patent transitions from planar electrode formation on the light-emitting surface to three-dimensional depression structures. Multiple depressions are formed in the active layer, allowing electrodes to be positioned in recessed areas rather than on the surface, thus preserving light extraction efficiency while enabling proper electrode formation for wire bonding
Solution Approach 2:
The patent applies different structural qualities to different regions of the active layer. Depressions are created in specific locations to accommodate electrodes, while the surrounding active layer remains intact for optimal light emission. This localized modification allows electrode formation without compromising overall light extraction efficiency
2Ease of manufacture
If a substantial portion of the active layer is removed for electrode formation, then the n-type electrode can be formed, but the surface area for heat dissipation is reduced
Solution Approach 1:
The patent uses vertical depression structures instead of horizontal surface removal. This allows electrodes to be formed in recessed areas while maintaining the full surface area of the active layer for heat dissipation. The depression depth provides the necessary space for electrode formation without sacrificing surface area
3Ease of manufacture
If the active layer surface area is reduced, then electrode formation is enabled, but the light emission surface area is lowered
Solution Approach 1:
The patent moves electrode formation from the two-dimensional surface plane to three-dimensional depression volumes. This allows the full surface area to remain available for light emission while providing recessed spaces for electrode placement and wire bonding operations
Solution Approach 2:
The patent implements localized depression structures only in specific areas where electrodes are needed, preserving the majority of the active layer surface area for light emission. The depressions are strategically positioned to minimize impact on the overall light-emitting surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves light extraction efficiency and heat dissipation by maintaining a larger active layer surface area for light emission and spreading current effectively, while also allowing for efficient electrical connections.
Implementation Method 1
an active layer formed between the first semiconductor layer and the second semiconductor layer
Data Source
AI summary
A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.