3D LED SiP Packaging Structure for Dense Reliable Interconnects
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Solution Overview
Problem
Current chip packaging technologies face challenges in miniaturization, high-density integration, and reliability, particularly in system-level packaging for LED chips, due to large area and thickness, complex procedures, and unreliable connections, which limit their application scope and integration capabilities.
Innovation Solution
A system-level packaging method for LED chips involves forming connecting pillar structures, packaging layers, and a rewiring layer to create a three-dimensional vertically stacked package, integrating multiple functional chips like ASIC and LED chips, and connecting them via metal lead wires to reduce area and power consumption, while ensuring reliable connections and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon-via (TSV) or silicon interposer technology is used for high-density integrated multi-chip packaging, then ultra-fine pins can be effectively interconnected, but the manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive silicon interposers and TSV structures with a cost-effective organic substrate and bump connection approach. The substrate uses standard PCB materials rather than specialized silicon, significantly reducing material costs while maintaining connection functionality through conventional solder bump technology.
Solution Approach 2:
The patent introduces an organic substrate as an intermediary carrier between chips and the final application. This substrate mediates the interconnection function, allowing multiple chips to be mounted and wired together using standard packaging techniques rather than requiring direct chip-to-chip silicon interposer connections.
2Adaptability or versatility
If fan-out packaging technology is used for integrated multi-chip packaging, then wafer reconstruction and rewiring can be achieved, but the package area and thickness increase due to limited wiring precision
Solution Approach 1:
The patent transitions from planar 2D chip arrangement to 3D vertical stacking by mounting chips on both the top and bottom surfaces of the substrate. This dimensional change allows multiple layers of chips to be integrated within a smaller footprint, reducing the overall package area while maintaining high connectivity through vertical interconnections.
Solution Approach 2:
The patent implements a nested structure where multiple chips are mounted on both sides of the substrate, with wiring layers embedded within the substrate thickness. The chips and wiring are nested within the compact substrate volume, achieving high integration density without increasing the external package dimensions.
3Ease of manufacture
If existing LED chip packaging structures (COB) are used, then low cost and simple structure are achieved, but connection reliability is poor
Solution Approach 1:
The patent replaces the traditional COB wire bonding mechanical system with a more reliable bump connection system. Solder bumps provide robust mechanical and electrical connections between chips and substrate, eliminating the fragility of thin wire bonds while maintaining manufacturing simplicity through standard reflow soldering processes.
4Adaptability or versatility
If system-in-package (SiP) is used to meet high packaging component and function demands, then integration capability improves, but the package occupies increasingly large area and thickness
Solution Approach 1:
The patent achieves high integration within small volume by utilizing 3D vertical stacking architecture. Chips are arranged in multiple layers on both sides of the substrate, with interconnections routed through vertical vias and embedded wiring layers, maximizing the use of vertical space rather than horizontal expansion.
Solution Approach 2:
The patent segments the packaging system into modular components: substrate, multiple chip layers, bump connections, and embedded wiring. This segmentation allows independent optimization of each component and facilitates high-density integration through systematic arrangement of discrete elements in three-dimensional space.
Data Source
AI summary
The present invention provides a SiP structure and method for a light emitting diode (LED) chip. The packaging structure includes: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a printed circuit board (PCB), and a third packaging layer. In the present invention, chips with a plurality of functions, including the first chip, the LED chip, and the like, are integrated into one packaging structure through fan-out system-level packaging, to meet a plurality of different system functional requirements and improve the performance of the packaging system. By the rewiring layer, a metal connecting pillar, a metal lead wire, and the like, the first chip, the LED chip, and the PCB are electrically connected, to achieve a three-dimensional vertically stacked package thereby effectively reducing the area of a SiP and improving the integration of the packaging system.