LED Solder Joint Thickness for CTE Mismatch Stress Relief

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing eutectic bonding method between LED chips and substrates in semiconductor packages results in a thin joint, leading to significant stress due to CTE mismatch, which can cause delamination during reliability tests, compromising the package's reliability.

Innovation Solution

A semiconductor package with a solder material of 5 to 40 um thickness is used to bond the LED chip to the substrate, providing a thicker joint that reduces stress and prevents delamination, while maintaining thermal conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If eutectic bonding is used to attach LED chip to substrate, then bonding strength is improved, but joint thickness becomes too thin (3-5 um) causing stress concentration and delamination

Engineering Contradiction:
Improvebonding strengthVSAvoidpackage reliability
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent changes the thickness parameter of the bonding joint from the conventional eutectic bonding thickness of 3-5 um to a thicker solder material layer of 10-50 um. This parameter change reduces stress concentration caused by CTE mismatch between LED chip and substrate, preventing delamination while maintaining bonding strength.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the thin eutectic bonding layer with a thicker solder material layer that can be easily applied and reflowed. The solder material serves as a more robust, stress-absorbing joint that compensates for thermal expansion differences without requiring precise control of thin layer formation.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If solder material thickness is increased to 5-40 um, then stress from CTE mismatch is reduced, but thermal conductivity may be affected

Engineering Contradiction:
Improvepackage reliabilityVSAvoidthermal conduction efficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent optimizes the solder material thickness to a specific range of 5-40 um, which is thick enough to reduce stress from CTE mismatch but thin enough to maintain acceptable thermal conductivity. This parameter optimization balances mechanical reliability with thermal performance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The solder material acts as a composite joint structure that combines the benefits of stress absorption (through increased thickness) with thermal conduction (through controlled thickness and material composition). The composite nature of the solder joint provides both mechanical and thermal functionality.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The thicker solder joint effectively mitigates stress from CTE mismatch, enhancing the reliability of the semiconductor package by preventing delamination and ensuring thermal conductive functionality.

Implementation Method 1

a solder material 24 having a thickness of 5 to 40 um is formed on the second surface treatment layer 21b... the LED chip 23 is mounted on and eutectically bounded to the substrate 10 with the first and second electrode pads 231, 232 of the LED chip 23 coupled to the first and second conductive pads 203a, 203b

Methodology Applied
Scientific EffectSoldering: Soldering

Implementation Method 2

the substrate with the chip is heated to an eutectic temperature so as for Au or Ag on the substrate and the Au—Sn alloy to diffuse mutually into each other, thereby changing the composition of the alloy

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 3

Next, the eutectic structure is solidified such that the die attachment process is completed

Methodology Applied
Scientific EffectSolidification: Freezing

Data Source

PatentUS8970053B2Semiconductor package having light-emitting-diode solder-bonded on first and second conductive pads separated by at least 75 UM
Publication Date: 2015.03.03 SILICONWARE PRECISION IND CO LTD
  • US8970053B2 patent drawing
  • US8970053B2 patent drawing
  • US8970053B2 patent drawing

AI summary

A semiconductor package and a fabrication method thereof are disclosed, which is characterized in that a solder material is used to bond an LED chip and a substrate so as to provide a thick joint between the substrate and the LED chip and hence reduce stresses generated between the LED chip and the substrate due to their CTE mismatch, thereby preventing delamination from occurring between the LED chip and the substrate after a reliability test.