Wafer-Level LED-TFT Bonding for Display Manufacturing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current display module manufacturing processes are inefficient and time-consuming, particularly when producing high-resolution display devices with integrated pixels, as they require individual pixel transfer and assembly, which prolongs the manufacturing time.

Innovation Solution

A method involving the bonding of a substrate with an LED array and a substrate with TFT cells at the wafer level, using a wafer bonding process to integrate LED cells and TFT cells, allowing for the easy manufacturing of display modules with multiple pixels without individual pixel transfer, thereby reducing manufacturing time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If individual pixel transfer and assembly methods are used, then manufacturing precision can be maintained, but manufacturing time is significantly prolonged

Engineering Contradiction:
Improvepixel assembly precisionVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges the LED cell array and TFT cell array into a single integrated substrate structure. The LED cells and TFT cells are formed on the same substrate through a unified manufacturing process, eliminating the need for separate transfer and assembly operations. This integration maintains manufacturing precision while dramatically reducing the time required for pixel assembly.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by pre-forming both LED cells and TFT cells on the same substrate in advance. The substrate is prepared with both types of cells already positioned and connected through conductive layers before final assembly, eliminating the need for time-consuming individual transfer operations during the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If wafer-level integration is implemented, then productivity is significantly improved, but device complexity increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidsubstrate structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the substrate into distinct functional regions: LED cell regions, TFT cell regions, and conductive layer regions. Each region is optimized for its specific function, with LED cells for light emission, TFT cells for signal processing, and conductive layers for electrical connection. This segmentation enables wafer-level manufacturing while managing complexity through functional zoning.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The substrate serves multiple functions simultaneously: it acts as both the foundation for LED cells and TFT cells, provides electrical connections through integrated conductive layers, and serves as the final assembly structure. This multi-functionality reduces the need for separate components and simplifies the overall device architecture despite the integrated design.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10797040B2Method of manufacturing display module using LED
Publication Date: 2020.10.06 SAMSUNG ELECTRONICS CO LTD
  • US10797040B2 patent drawing
  • US10797040B2 patent drawing
  • US10797040B2 patent drawing

AI summary

A method of manufacturing a display module includes preparing a first substrate structure including an light-emitting diode (LED) array containing a plurality of LED cells, electrode pads connected to the first and second conductivity-type semiconductor layers, and a first bonding layer covering the LED array; preparing a second substrate structure including a plurality of thin-film transistor (TFT) cells disposed on a second substrate, and each having a source region, a drain region and a gate electrode disposed therebetween, the second substrate structure being provided by forming a circuit region, in which connection portions disposed to correspond to the electrode pads are exposed to one surface thereof, and by forming a second bonding layer covering the circuit region, respectively planarizing the first and second bonding layers, and bonding the first and second substrate structures to each other.