Micro-interconnects for LED Packaging via Wafer-Level TSV Bonding

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Solution Overview

Problem

Traditional LED packaging methods, such as wire bonding, become increasingly challenging and costly as LED dies shrink in size, leading to difficulties in achieving efficient electrical connections and maintaining optical and electrical characteristics.

Innovation Solution

The implementation of wafer-level packaging using through-silicon vias (TSVs) and metal features on a silicon substrate, along with a conductive layer and interconnects, to provide direct electrical connections between LED dies and a packaging substrate, reducing assembly time and cost while enhancing bonding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wire bonding is used for LED packaging, then electrical connections can be established, but manufacturing difficulty and cost increase as LED die size decreases

Engineering Contradiction:
Improveease of electrical connectionVSAvoidbonding precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The packaging substrate is segmented into multiple regions with different metal features (bonding pads, through-silicon vias, interconnects) that enable simultaneous bonding of multiple LED dies in parallel, eliminating the sequential wire bonding process and improving manufacturing efficiency for small-form-factor LEDs

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Metal features (bonding pads and through-silicon vias) are introduced as intermediary conductive structures on the packaging substrate, enabling direct electrical connection between LED dies and substrate without requiring wire bonding, thus simplifying the manufacturing process for miniaturized LEDs

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If wire bonding is used for LED packaging, then electrical connections can be established, but assembly time increases with more bonding wires

Engineering Contradiction:
Improveease of electrical connectionVSAvoidassembly speed
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

Multiple electrical connection functions are merged into a single bonding step by integrating bonding pads, through-silicon vias, and interconnect structures on the packaging substrate, allowing simultaneous establishment of multiple electrical connections in parallel during one bonding process

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Metal features (bonding pads and through-silicon vias) are pre-formed on the packaging substrate before LED die bonding, enabling direct electrical connection without requiring sequential wire bonding operations, thus significantly reducing assembly time

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If longer bonding wires are used, then electrical connections can be established, but electrical and optical characteristics degrade

Engineering Contradiction:
Improveease of electrical connectionVSAvoidelectrical and optical performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Short, direct metal interconnects and through-silicon vias serve as intermediary conductive paths between LED dies and packaging substrate, eliminating the need for long bonding wires and thereby preserving electrical and optical characteristics while enabling direct bonding

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8653542B2Micro-interconnects for light-emitting diodes
Publication Date: 2014.02.18 ENNOSTAR CORP
  • US8653542B2 patent drawing
  • US8653542B2 patent drawing
  • US8653542B2 patent drawing

AI summary

The present disclosure provides a method of fabricating a light emitting diode (LED) package. The method includes bonding a plurality of separated light emitting diode (LED) dies to a substrate, wherein each of the plurality of separated LED dies includes an n-doped layer, a quantum well active layer, and a p-doped layer; depositing an isolation layer over the plurality of separated LED dies and the substrate; etching the isolation layer to form a plurality of via openings to expose portions of each LED die and portions of the substrate; forming electrical interconnects over the isolation layer and inside the plurality of via openings to electrically connect between one of the doped layers of each LED die and the substrate; and dicing the plurality of separated LED dies and the substrate into a plurality of LED packages.