LED with Vias and Patterned Passivation for Light Extraction
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Solution Overview
Problem
Conventional light emitting diodes (LEDs) suffer from reduced luminous efficiency due to light being screened out by electrodes, particularly in flip-chip packaging where a significant portion of the die is non-illuminating, limiting their light intensity.
Innovation Solution
The LED design incorporates a substrate with distinct regions, semiconductor layers, vias, and a patterned passivation layer to allow for electrical isolation and full exposure of the light-emitting layer, eliminating non-illuminating regions and enhancing light transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional wire bonding packaging is used, then the structure is simple and assembly is easy, but the electrode screens out part of the light reducing luminous efficiency
Solution Approach 1:
The substrate is divided into a first region and a second region, with vias formed in the first region to create separate conductive paths. This segmentation allows the electrode to be electrically connected to the semiconductor layer without covering the light-emitting region, thus maintaining luminous efficiency while achieving electrical connection.
Solution Approach 2:
The patent transitions from planar electrode placement to a three-dimensional structure with vias penetrating through the substrate. This dimensional change allows electrical connection through the substrate thickness rather than requiring surface-level electrode coverage, eliminating light screening while maintaining electrical connectivity.
2Loss of energy
If flip chip packaging is used, then light emitted upwardly is not screened out, but a significant portion of the die becomes non-illuminating limiting light intensity
Solution Approach 1:
The substrate is segmented into a first region with vias for electrical connection and a second region that remains fully illuminating. This segmentation allows the light-emitting layer to be completely exposed while electrical connections are established through the vias in the first region, eliminating non-illuminating areas.
Solution Approach 2:
The electrical connection function is extracted from the planar electrode surface and relocated to vertical vias penetrating the substrate. This extraction allows the light-emitting layer to be fully exposed without being covered by electrodes, eliminating non-illuminating regions while maintaining electrical connectivity.
3Reliability
If electrodes are placed to provide electrical connection, then electrical conductivity is achieved, but light transmission is obstructed reducing output intensity
Solution Approach 1:
The electrical connection path is moved from the horizontal plane to the vertical dimension through vias penetrating the substrate. This dimensional transition allows electrodes to connect to the semiconductor layer through the substrate thickness without covering the light-emitting region, maintaining electrical reliability while eliminating light obstruction.
Solution Approach 2:
The substrate with vias acts as an intermediary structure that enables electrical connection between the electrode and semiconductor layer without requiring direct surface contact. This intermediary approach allows light to pass through the substrate region while electrical connections are established through the via pathways.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves luminous efficiency by providing multiple conductive paths and minimizing light obstruction, resulting in enhanced light output without the need for wire bonding or die bonding processes.
Implementation Method 1
The plurality of vias are located in the first region and penetrate through the second semiconductor layer and the light-emitting layer to expose part of the first semiconductor layer. The first metal layer is located in the first region and electrically contacted with the first semiconductor layer through the plurality of vias.
Implementation Method 2
the light-emitting layer is formed on the first semiconductor layer
Implementation Method 3
The patterned passivation layer is sandwiched in between the second semiconductor layer and the first metal layer for electrically isolating the first metal layer from the second semiconductor layer and the light-emitting layer.
Data Source
AI summary
A light emitting diode and a method of the same are provided. The light emitting diode includes a substrate with a first region and a second region, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer. The light emitting diode further includes a plurality of vias, a first metal layer, a second metal layer, and a patterned passivation layer interposed between the second semiconductor layer and the first metal layer. The plurality of vias are located in the first region and penetrate through the second semiconductor layer and the light-emitting layer to expose part of the first semiconductor layer. The first metal layer is located in the first region, and electrically contacted with the first semiconductor layer through the plurality of vias. The second metal layer is located in the second region, and electrically contacted with the second semiconductor layer and electrically insulated from the first metal layer. The patterned passivation layer is configured to electrically isolate the first metal layer from the second semiconductor layer and the light-emitting layer.