Length-Aware Local Tiling in Sparse Attention Transformers
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Solution Overview
Problem
Transformer neural networks face efficiency bottlenecks due to quadratic computational complexity in attention mechanisms, particularly in longer sequence scenarios, limiting their application in tasks like long-document generation and video/image generation.
Innovation Solution
The method involves length-aware local tiling in sparse attention modules, where a heterogeneous device divides a transformed sparsity mask into tiles, loads effective tiles into shared memory, and performs sparse-dense matrix multiplication using GPU kernels, optimizing computation by leveraging shared memory and reducing unnecessary calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional dense attention mechanism is used in transformer, then comprehensive attention computation is achieved, but computational complexity grows quadratically with sequence length
Solution Approach 1:
The patent applies segmentation by dividing the attention computation into sparse and dense parts. The sparsity mask is segmented to identify zero-element regions, allowing the attention mechanism to process only non-zero elements through sparse computation while maintaining the ability to compute comprehensive attention when needed. This resolves the contradiction by reducing computational complexity without completely sacrificing attention completeness.
Solution Approach 2:
The patent implements local quality by applying different computation strategies to different regions of the attention matrix. Regions with zero elements in the sparsity mask use sparse computation, while regions with non-zero elements use dense computation. This localized approach optimizes computational complexity for each region based on its characteristics, resolving the contradiction between comprehensive computation and computational efficiency.
2Productivity
If sparse attention mechanism is used to reduce computational complexity, then processing speed improves, but memory access efficiency deteriorates due to scattered memory access patterns
Solution Approach 1:
The patent segments the sparsity mask into tiles and processes each tile independently. This segmentation allows the system to identify contiguous regions of zero elements and skip entire tile blocks, transforming scattered memory access into more structured access patterns. The segmentation principle resolves the contradiction by organizing sparse computation into manageable units that improve memory access efficiency.
Solution Approach 2:
The patent introduces tiling as an additional dimensional organization for the sparsity mask, dividing it into grid-like tiles. This dimensional change allows the system to exploit spatial locality and cache efficiency by processing tiles in a systematic order, converting the problematic scattered access pattern into a more regular, cache-friendly access pattern while maintaining processing speed benefits.
3Productivity
If GPU shared memory is utilized for tiling, then computation speed increases, but shared memory capacity is limited
Solution Approach 1:
The patent segments the attention computation into tile-sized units that can fit within GPU shared memory capacity. By dividing the large sparsity mask into smaller tiles, the system can load multiple tiles into shared memory concurrently, maximizing the utilization of limited shared memory capacity while maintaining high computation speed through parallel processing of multiple tiles.
Solution Approach 2:
The patent loads multiple tiles into shared memory simultaneously, which may exceed the strict minimum requirements for processing a single tile. This partial or excessive action of pre-loading multiple tiles into shared memory reduces the need for repeated global memory accesses during computation, thereby increasing computation speed while efficiently utilizing the available shared memory capacity.
Data Source
AI summary
A method and an apparatus for length-aware local tiling in a sparse attention module in a transformer in heterogeneous devices are provided. The method includes that a heterogeneous device including one or more GPUs: divides a transformed sparsity mask into a plurality of first tiles and obtaining one or more effective first tiles from the plurality of first tiles, where each effective first tile includes at least one non-zero element; loads the one or more effective first tiles into a shared memory in the one or more GPUs and loads a plurality of elements in a first matrix corresponding to the one or more effective first tiles into the shared memory; and performs multiplication by a first sampled dense-dense matrix multiplication (SDDMM) kernel in the sparse attention module in the transformer by fetching the one or more effective first tiles and the plurality of elements from the shared memory.