Level-Sensitive Comparator Logic for Clean Square-Wave Extraction
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Solution Overview
Problem
Existing level-sensitive comparing devices, which convert sinusoidal waves to square waves, face challenges in ensuring a high-quality square wave output due to the large area requirements of analog peak detector circuits, leading to inefficiencies in clock extraction systems.
Innovation Solution
A level-sensitive comparing device utilizing digital components, including comparators and a determination circuit composed of digital components only, to compare input signals with reference levels and determine the output, thereby eliminating the need for analog peak detectors and reducing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog peak detector circuit is used to determine the peak value of the input signal, then the level sensitivity can be achieved, but the circuit area becomes large due to the requirement of rectifiers and capacitors
Solution Approach 1:
The patent replaces the analog peak detector circuit with a digital determination circuit. Instead of using analog components like rectifiers and capacitors to detect peak values, the invention uses digital comparators to compare the input signal with reference levels and a digital logic circuit (comprising AND gates, OR gates, and NOT gates) to determine whether the peak value exceeds the reference level. This substitution of analog detection with digital comparison and logic operations significantly reduces the circuit area while maintaining level sensitivity.
2Device complexity
If a related-art clock extractor is used without level sensitivity, then the circuit design is simple, but the output waveform cannot ensure an ideal square wave when the peak value drops below a certain level
Solution Approach 1:
The patent implements a feedback mechanism through the determination circuit that monitors the comparison results from multiple comparators. When the input signal peak value drops below the reference level, the determination circuit detects this condition through the logic gates and generates a control signal to prevent the output from becoming an ideal square wave. This feedback-based level sensitivity detection ensures that the clock extractor maintains high output waveform quality by adapting its behavior based on the input signal conditions.
Data Source
AI summary
A level sensitive comparing device includes: a first comparator, a second comparator, and a determination circuit. The first comparator is arranged for comparing an input signal with a first reference level to generate a first comparison signal. The second comparator is arranged for comparing the input signal with a second reference level to generate a second comparison signal, wherein the second reference level is different from the first reference level. The determination circuit is coupled to the first comparator and the second comparator, and is arranged for determining whether the first comparison signal is allowed to appear at an output of the level sensitive comparing device according to at least the first comparison signal and the second comparison signal, wherein the determination circuit is composed of digital components only.