Level-Crossing ADC Sampling With Asynchronous Reset Control
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Solution Overview
Problem
Existing analog-to-digital converters in wireless sensor nodes face challenges in minimizing power consumption, especially for biological signals with sparse data, due to the need for large capacitors and high SNDR requirements, which increase area and power consumption, and are affected by comparator offset and leakage errors.
Innovation Solution
A system and method using level-crossing based sampling with asynchronous resets and shared amplifiers, capacitive DACs, and additional trigger signals to minimize hold time requirements and reduce area, while compensating for comparator offsets and leakage errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If level-crossing sampling is used to reduce data transmission for sparse biological signals, then transmitter power consumption is reduced, but comparator offset and leakage errors increase
Solution Approach 1:
The patent applies preliminary action by performing offset calibration of the comparators before the actual signal conversion process. The calibration phase compensates for comparator offsets in advance, ensuring that during the level-crossing sampling operation, the accumulated offset errors remain within acceptable limits. This preliminary calibration enables the system to maintain high SNDR while operating in low-power level-crossing mode.
Solution Approach 2:
The patent implements periodic action by continuously monitoring the accumulated offset errors during level-crossing sampling and periodically updating the calibration values. This periodic recalibration approach allows the system to maintain measurement precision over extended operation periods while keeping the comparators in a low-power state most of the time, thus reducing overall power consumption.
2Measurement precision
If large capacitors are used to meet long hold time requirements for low frequency signals, then measurement accuracy is improved, but device area increases
Solution Approach 1:
The patent applies dynamics by making the capacitor configuration adaptive rather than static. The system dynamically selects and switches between multiple capacitors based on the input signal frequency and the required hold time. For low-frequency signals requiring long hold times, larger capacitors are activated, while for higher-frequency signals, smaller capacitors suffice. This dynamic adaptation allows the system to achieve the required measurement precision without permanently allocating large capacitor areas.
Solution Approach 2:
The patent implements parameter changes by varying the effective capacitance value based on operating conditions. The system changes the capacitor configuration parameters (which capacitors are connected and their combination) according to the signal characteristics and required hold time. This parameter adaptation enables the system to meet accuracy requirements for low-frequency signals with long hold times while minimizing the total capacitor area by not using large capacitors for all operating conditions.
3Reliability
If continuous sampling is performed to monitor biological signals, then signal detection capability is improved, but power consumption increases
Solution Approach 1:
The patent applies segmentation by dividing the continuous signal monitoring into discrete level-crossing events. Instead of continuously sampling at every clock cycle, the system segments the monitoring process to activate the comparators and sampling circuitry only when the input signal crosses predefined threshold levels. This segmentation approach maintains reliable signal detection capability for sparse biological events while dramatically reducing power consumption during periods when no signal crossings occur.
Solution Approach 2:
The patent implements this principle by using a calibration mechanism that is activated only when needed rather than continuously. The offset calibration function operates as a short-lived, on-demand process that corrects comparator errors only when accuracy is required, rather than maintaining continuous calibration. This approach ensures reliable signal detection while minimizing the energy cost of calibration operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and area requirements, maintains high SNDR, and mitigates leakage-induced errors, enabling efficient conversion of sparse biological signals with lower power consumption.
Implementation Method 1
the use of capacitive DACs
Implementation Method 2
an amplifier configured to amplify an error signal comprising a difference between the analog input signal and the reference signal
Implementation Method 3
a level-crossing based sampling circuit comprising a first comparator configured to compare the error signal with respect to a first reference level, and a second comparator configured to compare the error signal with respect to a second reference level
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3B
AI summary
A system (200) for analog-to-digital signal conversion is provided. The system comprises an analog input signal (201), a digital-to-analog converter (202) configured to generate a reference signal (203), and an amplifier (206) configured to amplify an error signal comprising a difference between the analog input signal (201) and the reference signal (203). The system further comprises a level-crossing based sampling circuit (220) comprising a first comparator (214) configured to compare the error signal with respect to a first reference level, and a second comparator (215) configured to compare the error signal with respect to a second reference level, thereby generating event-based reset signals (221) corresponding to a plurality of sampling instances in order to reset the digital-to-analog converter (202) and further to shift the first reference level and the second reference level through the digital-to-analog converter (202). Moreover, the system comprises a trigger circuit (223) configured to generate reset signals (224) asynchronous to the event-based reset signals (221) in order to reset the digital-to-analog converter (202).