Level-Dependent ECC Coding in Multi-Level NAND Memory
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Solution Overview
Problem
As NAND memory cell storage technologies progress to multi-level cells, errors increase due to shifting memory states and complex encoding schemes, leading to varying bit error rates across different memory levels, necessitating effective error correction coding tailored to each level.
Innovation Solution
A method for level-dependent error correction code protection in multi-level non-volatile memory, where the coding rate for ECC codewords is adjusted based on attributes of each multi-level page, using an ECC encoder to generate codewords with variable parity sizes, ensuring balanced bit error rates across page levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells (MLCs), tri-level cells (TLCs), and quad-level cells (QLCs) are used to store multiple bits per memory cell, then storage capacity increases, but bit error rate increases due to memory state shifts and spreading
Solution Approach 1:
The patent applies different ECC coding rates to different memory levels (pages) within the same multi-level cell structure. Specifically, lower pages use coding rate 1/5 while upper pages use coding rate 1/3, tailoring the error correction strength to the local BER characteristics of each page rather than applying a uniform coding rate to all pages.
Solution Approach 2:
The patent changes the ECC coding rate parameter based on the memory level being written. The system dynamically selects between coding rates 1/5 and 1/3 depending on which pages are being written, thereby adjusting the error correction capability to match the observed BER characteristics of different memory levels.
2Quantity of substance
If complex encoding schemes are used in QLC memory cells to store four bits per cell, then storage density increases, but error correction requirements become more complicated and varying BERs occur across different memory levels
Solution Approach 1:
The patent segments the error correction approach by dividing the QLC memory into different page levels (lower, middle, upper) and applying different ECC coding rates to each segment. This segmentation allows the system to handle the varying BER characteristics of different pages independently, simplifying the overall error correction strategy compared to applying a single complex coding scheme to all pages.
Solution Approach 2:
Different ECC coding rates are applied to different page levels within the QLC structure. Lower pages with higher BER use coding rate 1/5 for stronger error correction, while upper pages with lower BER use coding rate 1/3, optimizing error correction effectiveness for each local region rather than using a uniform approach.
3Measurement precision
If more memory states are read to ascertain a cell's memory state in certain levels, then data accuracy improves, but bit error rate increases due to more read points
Solution Approach 1:
The patent changes the ECC coding rate parameter based on the memory level being written. The system dynamically selects between coding rates 1/5 and 1/3 depending on which pages are being written, thereby adjusting the error correction capability to match the observed BER characteristics of different memory levels.
Data Source
AI summary
A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.