On-Chip Level Detector Calibration Using Replica Bias Circuit
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Solution Overview
Problem
In wireless communication systems, inaccuracies in power amplification circuit level detectors lead to reduced output power, limiting the transmitter's range due to uncertainties in measured power levels, especially when integrated with other RF circuitry in shrinking semiconductor geometries, which restricts the input power range for linear amplification.
Innovation Solution
A method and system for calibrating level detectors on-chip using a replica bias circuit with no input AC voltage, eliminating zero input offset voltage by combining offset voltages and utilizing known input voltages generated by clipping a VCO signal, applied to buffers, to improve accuracy in transmit power control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If level detector calibration is performed using traditional external methods, then measurement precision may be improved, but device complexity and manufacturing difficulty increase due to requiring external calibration equipment and off-chip procedures
Solution Approach 1:
The calibration function is merged with the level detector circuit itself by integrating a replica bias circuit on the same chip. The replica circuit generates calibration voltages that are combined with the level detector output through a summing node, eliminating the need for external calibration equipment and enabling self-contained calibration functionality
Solution Approach 2:
The replica bias circuit pre-generates calibration voltages corresponding to different output power levels before they are needed for calibration. These calibration voltages are stored and made available when calibration is required, allowing the level detector to be calibrated without requiring external equipment during the calibration process
2Reliability
If output power of PA is reduced below FCC limit to account for level detector uncertainty, then reliability of power control is improved, but transmitter range decreases due to lower output power
Solution Approach 1:
The calibration system establishes an accurate feedback loop between the level detector and the PA control circuitry. By calibrating the level detector to precisely measure actual output power levels, the system receives accurate feedback about transmitter power, enabling reliable power control at maximum FCC limits without excessive reduction margins
Solution Approach 2:
The calibration process changes the operational parameters of the level detector by applying known calibration voltages from the replica bias circuit. This adjusts the detector's measurement characteristics to match actual output power levels, improving measurement accuracy and enabling operation at higher power levels with confidence
3Adaptability or versatility
If PA is integrated with other RF circuitry in shrinking semiconductor geometries, then device integration is improved, but manufacturing precision deteriorates due to process variations affecting level detector accuracy
Solution Approach 1:
A replica bias circuit is created as a copy of the level detector's biasing circuitry, positioned nearby on the same chip. This replica circuit experiences identical process variations and is used to generate calibration voltages that compensate for those variations, effectively canceling out manufacturing precision issues affecting the level detector
Solution Approach 2:
The calibration function is implemented locally within the PA circuit block using the replica bias circuit and summing node integrated into the same circuit architecture. This local implementation ensures that calibration voltages are generated under the same local conditions and process variations as the level detector, improving compensation effectiveness
Data Source
AI summary
Methods and systems for level detector calibration are disclosed and may comprise calibrating a level detector integrated on-chip to eliminate an associated zero input offset voltage utilizing a replica bias circuit with no input ac voltage at the level detector or the replica bias circuit. The offset voltages of the level detector and the replica bias circuit may be combined to eliminate the associated zero input offset voltage of the level detector. The output signal may be generated by a difference of output signals from the level detector and the replica bias circuit. The level detector and the replica bias circuit may be biased utilizing a similar bias voltage. A plurality of known input voltages may be utilized to generate a corresponding plurality of output voltages of the level detector, generating a corrected transfer function that may be used to accurately set a transmitter power level.