Level-Converting Flip-Flops for Contention-Free Low-Swing Clocking
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Solution Overview
Problem
Conventional double level-converting flip-flops for low-swing clocking and clustered voltage scaling are power-inefficient and prone to contention due to their ratioed design, which requires precise balancing of transistor strengths and sizes, making them less robust and slower.
Innovation Solution
A family of contention-free, non-ratioed level converting flip-flops that combine data storage and level conversion functions, allowing for efficient low-swing clocking and clustered voltage scaling by sharing positive feedbacks, reducing timing and power overheads, and enhancing robustness to process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional ratioed level converting flip-flops are used, then level conversion function is achieved, but the design is slow and power-inefficient due to contention
Solution Approach 1:
The patent extracts and removes the contention-prone ratioed design elements from the level converting flip-flop. By eliminating the need for precise transistor strength balancing, the design removes the source of contention that causes both power waste and delay, achieving both power efficiency and fast operation simultaneously.
Solution Approach 2:
The patent changes the fundamental design parameter from ratioed (requiring precise transistor size ratios) to non-ratioed (contention-free). This parameter change transforms the circuit operation mode, eliminating the trade-off between power consumption and speed by removing the contention mechanism entirely.
2Reliability
If conventional ratioed level converting flip-flops are used, then level conversion is achieved, but robustness is reduced due to dependence on precise transistor balancing
Solution Approach 1:
The patent extracts the problematic ratioed design constraint that requires precise transistor balancing. By removing this constraint, the design achieves robustness against process variations without requiring complex design adjustments, as the contention-free structure inherently tolerates parameter variations.
Solution Approach 2:
The patent changes the design parameter from ratioed to non-ratioed, which fundamentally improves robustness to process variations. This parameter change eliminates the sensitivity to transistor size and strength variations, making the circuit more reliable without increasing design complexity.
3Power
If double level-converting flip-flop is implemented with separate data storage and level conversion, then level conversion function is achieved, but power efficiency is reduced
Solution Approach 1:
The patent merges the data storage function of the flip-flop with the level conversion function into a single integrated structure. This combination eliminates the need for separate level conversion circuits, reducing power consumption while maintaining the necessary functionality. The merged design achieves both storage and level conversion in one contention-free circuit.
Solution Approach 2:
The patent creates a multi-functional flip-flop that simultaneously performs data storage and level conversion. This universal circuit element eliminates the need for separate dedicated level conversion circuits, improving power efficiency by reducing the total number of active components and their associated power consumption.
Data Source
AI summary
The present invention includes a family of level converting flip-flops that accepts data and clock inputs at a lower voltage level while producing data outputs at a higher voltage level. These flip-flops enable fine-grained dual supply voltage techniques such as low-swing clocking (distributing the clock signal at a lower voltage level) and clustered voltage scaling (CVS). The level conversion is accomplished in a very efficient manner by sharing the positive feedbacks inside a flip-flop for both storage and level conversion. Additionally, the presented flip-flops are contention-free and non-ratioed, thus having reduced timing and power overheads due to the level conversion function.