Level Shift Circuit Assist Timing for Lower Transistor Stress
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Solution Overview
Problem
Existing level shift circuits face issues with insufficient assist operation speed and voltage stress on transistors due to premature termination of assist operations and simultaneous transistor switching, which becomes problematic with the miniaturization of manufacturing processes.
Innovation Solution
A level shift circuit design that includes specific transistor configurations and inverters to delay the termination of assist operations, ensuring sufficient assist time and preventing simultaneous transistor switching, thereby reducing voltage stress and enhancing assist operation effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the assist operation is terminated when the output signal reaches Vcc, then the circuit operation is simplified, but the assist operation effectiveness is insufficient and speedup is inadequate
Solution Approach 1:
The patent extends the assist operation beyond the conventional termination point (when output reaches Vcc) by keeping the assist transistor conducting until the output reaches the higher voltage level (Vpp or Vdd2). This preliminary continuation of the assist action ensures complete and effective level shifting, resolving the contradiction between simplified operation and adequate assist effectiveness.
2Area of moving object
If transistors are miniaturized to reduce device size, then integration density is improved, but voltage stress on transistors becomes excessive and reliability deteriorates
Solution Approach 1:
The patent introduces a multi-stage transistor arrangement where the assist transistor is divided into multiple sections (first assist transistor and second assist transistor) with intermediate nodes. This segmentation distributes the voltage stress across multiple devices rather than concentrating it on a single miniaturized transistor, thereby maintaining reliability while enabling further miniaturization for improved integration density.
3Speed
If the assist transistor remains ON during the entire transition, then the speedup is maximized, but voltage stress on the transistor increases due to simultaneous switching
Solution Approach 1:
The assist transistor is segmented into multiple transistors arranged in series, with their gate signals phased differently. This segmentation allows the overall assist function to continue (maintaining speedup) while distributing the voltage stress across multiple devices, preventing any single transistor from experiencing excessive stress during simultaneous switching.
Solution Approach 2:
The patent employs phased gate signals for the segmented assist transistors, creating a periodic or sequential switching pattern. This periodic action ensures continuous assist functionality (maintaining high speed) while alternating the stress distribution across different transistor segments, thereby reducing peak voltage stress on any individual transistor.
Data Source
AI summary
A level shift circuit includes first to fourth n-type transistors, first and second p-type transistors, and first and second inverters. The first n-type transistor receives an input signal at its gate and has a drain connected to an inverted output node. The first p-type transistor is placed between a third power supply and the inverted output node. The second n-type transistor receives an inverted input signal at its gate and has a drain connected to an output node. The second p-type transistor is placed between the third power supply and the output node. The third n-type transistor is between the inverted output node and an inverted input node, and the first inverter between the drain and gate of the third n-type transistor. The fourth n-type transistor is between the output node and an input node, and the second inverter between the drain and gate of the fourth n-type transistor.