Cross-Coupled Level Shift Circuit for High-Voltage Breakdown Protection
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Solution Overview
Problem
Conventional cross-coupled level shift circuits in NAND-type flash memory devices face challenges with high-voltage breakdown when operating at voltages exceeding 8 V, requiring additional ion implantation to improve breakdown voltage, which increases process costs and circuit area.
Innovation Solution
A level shift circuit design incorporating specific transistor configurations, including cross-connected first and second conductivity type transistors, third and fourth transistors with constant voltage gates, and seventh and eighth transistors supplying constant voltage to back gates, to prevent voltage exceeding 8 V between drain and source or drain and well, thereby maintaining transistor size and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage VREAD is increased to 8V to support multi-level data storage, then the read capability is improved, but the breakdown voltage requirement for transistors increases beyond the conventional 8V limit
Solution Approach 1:
The level shift circuit is divided into multiple stages with intermediate nodes. The first level shift circuit shifts voltage from VREAD (8V) to an intermediate level, and the second level shift circuit further shifts it to VREADH (10V). This segmentation allows each transistor stage to handle only portion of the total voltage swing, preventing any single transistor from experiencing excessive voltage stress that would cause breakdown.
Solution Approach 2:
Intermediate voltage nodes are introduced between the input and output of the level shift circuit. These intermediate nodes act as mediators that gradually transition the voltage level rather than applying the full voltage difference across a single transistor. The cross-coupled configuration with intermediate nodes ensures that no transistor experiences more than 8V stress while achieving 10V output.
2Strength
If ion implantation is added to improve transistor breakdown voltage, then the breakdown voltage is enhanced, but the process cost increases
Solution Approach 1:
The circuit architecture is modified to change the voltage distribution parameters across transistors. By reconfiguring the level shift circuit with cross-coupled transistors and intermediate nodes, the voltage stress parameters are optimized so that no transistor experiences more than 8V, eliminating the need for costly ion implantation processes while maintaining adequate breakdown voltage margins.
3Strength
If additional ion implantation is performed to enhance breakdown voltage, then the transistor strength is improved, but the circuit area increases
Solution Approach 1:
The level shift function is segmented across multiple transistor pairs working in parallel through cross-coupling. This segmentation allows the use of standard breakdown voltage transistors without requiring area-expanding ion implantation, as the voltage stress is distributed across multiple devices rather than requiring oversized single transistors.
Data Source
AI summary
A gate and the other end of the current path of first and second transistors are cross-connected. A third transistor is inserted to the other end of the current path of the first transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. A fourth transistor is inserted to the other end of the current path of the second transistor, and a gate is supplied with a constant voltage, and further, one end of the current path and well are connected. Fifth and sixth transistors are connected to the other end of the current path of the third and fourth transistors, and a gate is complementarily supplied with an input signal. Seventh and eighth transistors are connected to a back gate (well) of the third and fourth transistors, and a gate is complementarily supplied with an output signal.