Level-Shift Buffer Amplifier Circuit for PVT-Stable Output

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Solution Overview

Problem

Prior art buffer amplifier circuits face significant challenges in maintaining a constant level shift due to variations in PVT (process, temperature, and supply voltage) which require large adjustments in current, affecting bandwidth and output resistance.

Innovation Solution

Incorporating a variable resistance that is a function of a control voltage, allowing for adjustments in resistance to counteract PVT variations, implemented using transistors such as NMOS or PMOS in series or parallel configurations with source followers, to maintain a constant level shift.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If current adjustment is used to compensate for VT variation, then level shift constancy is improved, but bandwidth and output resistance vary significantly

Engineering Contradiction:
Improvelevel shift constancyVSAvoidbandwidth and output resistance stability
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent changes the resistance parameter of the current source transistor dynamically to compensate for VT variations. By adjusting the resistance value based on detected level shift deviations, the system maintains constant level shift without requiring large current adjustments, thus preserving bandwidth and output resistance characteristics.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the level shift is continuously monitored and compared against a reference value. The error signal generated from this comparison is used to adjust the resistance of the current source, creating a closed-loop control system that maintains constant level shift while avoiding the side effects of direct current adjustment.

Inventive Principle:
Principle #23Feedback

2Stability of the object's composition

If large current adjustment is applied to compensate for PVT variations, then level shift constancy is improved, but device complexity and current control difficulty increase

Engineering Contradiction:
Improvelevel shift constancyVSAvoidcurrent control complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

Instead of adjusting current directly, the patent changes the resistance parameter of the current source transistor. This approach achieves level shift compensation through resistance modulation rather than current control, simplifying the control mechanism and reducing device complexity while maintaining level shift constancy across PVT variations.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If variable resistance is introduced to counteract PVT variations, then level shift precision is improved, but device complexity increases

Engineering Contradiction:
Improvelevel shift precisionVSAvoidcircuit structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs a self-service mechanism where the circuit automatically adjusts its own resistance parameter in response to detected level shift deviations. The feedback loop within the circuit enables autonomous compensation for PVT variations without requiring external control, thereby improving level shift precision while minimizing the increase in device complexity through self-regulation.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11114986B2Constant level-shift buffer amplifier circuits
Publication Date: 2021.09.07 OMNI DESIGN TECH
  • US11114986B2 patent drawing
  • US11114986B2 patent drawing
  • US11114986B2 patent drawing

AI summary

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.