Level Shift Circuit With Clamp Bypass for Low-Voltage Reliability
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Solution Overview
Problem
Existing level shift circuits face high voltage stress and breakdown issues due to reverse voltage across transistors, particularly when operating at low voltages, leading to transistor damage and circuit failure.
Innovation Solution
A level shift circuit design incorporating a high voltage circuit, a clamp circuit to prevent transistor breakdown, and a bypass circuit that connects between the input circuit and high voltage circuit, allowing the circuit to operate effectively by managing voltage levels and avoiding excessive stress on transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level shift circuit is used to shift voltage levels, then the circuit can transfer signals between different voltage domains, but the transistors experience high voltage stress and breakdown due to reverse voltage across drain and gate
Solution Approach 1:
The patent introduces an intermediary transistor (the third PMOS transistor) that acts as a buffer between the high voltage terminal and the gate of the first PMOS transistor. This intermediary device transfers the gate control signal while isolating the high voltage from the sensitive gate terminal, thereby preventing breakdown while maintaining the voltage level shifting function.
Solution Approach 2:
The patent divides the voltage level shifting function into multiple stages using separate transistor circuits for different voltage domains. The first PMOS transistor handles the high voltage domain, the second PMOS transistor handles the low voltage domain, and the third PMOS transistor bridges these domains. This segmentation allows each transistor to operate within its safe voltage limits while collectively achieving the overall voltage level shifting.
2Reliability
If the high voltage terminal is controlled to prevent transistor breakdown, then transistor reliability improves, but the circuit loses adaptability to operate at low voltages
Solution Approach 1:
The patent creates a dynamic voltage level shifting circuit where the third PMOS transistor automatically adjusts its conduction state based on the voltage levels at its source and gate terminals. When the high voltage terminal needs to drive the low voltage domain, the third transistor conducts to transfer the signal. When operating at low voltages, the voltage difference conditions prevent excessive stress while maintaining functionality. This dynamic behavior enables the circuit to adapt to different voltage operating conditions without requiring manual control.
3Reliability
If a clamp circuit is added to prevent transistor breakdown, then transistor reliability improves, but the device complexity increases
Solution Approach 1:
The third PMOS transistor serves multiple functions simultaneously: it acts as a gate driver for the first PMOS transistor, provides voltage level shifting, and inherently limits the voltage stress on the first transistor's gate through its own voltage-current characteristics. By making this single device multi-functional, the patent achieves reliable protection without adding separate clamp circuits or protection devices, thereby avoiding increased complexity.
Data Source
AI summary
A level shift circuit includes a high voltage circuit, a clamp circuit, an input circuit, and a bypass circuit. The high voltage circuit is electrically connected to a high voltage terminal. The clamp circuit can prevent the transistors of the high voltage circuit from high voltage stress when a voltage level of the high voltage terminal is greater than a voltage level of a voltage source. The bypass circuit is used to bypass the clamp circuit when a voltage level of the high voltage terminal is smaller than a voltage level of transistor breakdown voltages.