Level Shift Circuit Delay Equalization for Symmetric Transitions
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Solution Overview
Problem
Conventional level shifters exhibit unequal transition delays when switching between high and low states, with faster High-to-Low transitions compared to Low-to-High transitions, leading to unsatisfactory equalization of delay times.
Innovation Solution
A delay equalization circuit is introduced that generates signals directly and inversely related to the input signal state, using a reset dominant latch and data selection circuit to substitute signals during slow delay periods, ensuring equal and reduced output delays by controlling the output voltage reference nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifter circuit is used, then High-to-Low transitions are fast, but Low-to-High transitions are slow
Solution Approach 1:
The patent applies preliminary action by generating a preliminary signal before the slow Low-to-High transition occurs. This preliminary signal is generated in advance and used to control the output during the transition period, effectively preparing the system for the upcoming state change and reducing the overall transition delay.
Solution Approach 2:
The patent introduces an intermediary signal (the preliminary signal) that mediates between the input signal and the output control. This intermediary signal acts as a bridge, allowing the system to anticipate and prepare for state transitions, thereby equalizing the delays between High-to-Low and Low-to-High transitions.
2Device complexity
If conventional level shifter circuit is used, then circuit structure is simple, but output delays are unequal
Solution Approach 1:
The patent adds a preliminary signal generation mechanism that operates in advance of the main transition. This additional circuitry, while increasing complexity, enables the system to predict and prepare for state changes, thereby equalizing output delays without requiring major structural overhauls.
Solution Approach 2:
The patent implements a feedback mechanism where the preliminary signal is generated based on the current state and used to control the output during transitions. This feedback loop allows the system to continuously adjust and equalize delays, maintaining timing symmetry despite the added circuit complexity.
3Ease of manufacture
If conventional level shifter circuit is used, then circuit implementation is straightforward, but transition delays are asymmetrical
Solution Approach 1:
The patent incorporates preliminary signal generation that can be implemented using standard logic circuit elements. This approach maintains ease of manufacture by using conventional components and techniques, while the preliminary action mechanism ensures precise delay equalization and symmetrical transitions.
Solution Approach 2:
The patent adjusts timing parameters by introducing the preliminary signal with specific timing characteristics. By changing the temporal parameters of signal generation and using this preliminary signal to control transitions, the system achieves symmetrical delay characteristics while maintaining straightforward circuit implementation.
Data Source
AI summary
Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input signal from a high state to a low state, the third signal is selected for controlling the output until the first signal attains a high state. The first signal is selected for controlling the output when it has reached a high state after the input signal transition. The first signal remains selected upon transition of the input signal from a high state to a low state. Thus, output delays are equalized and reduced to the shortest delay.