Level Shift Circuit Timing Alignment for Duty Ratio Stability
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Solution Overview
Problem
Level shift circuits designed to increase signal amplitude often suffer from timing differences between changes in input signal logic levels, leading to duty ratio deviations, which can reduce the effective data width in semiconductor devices.
Innovation Solution
The semiconductor device incorporates a level conversion circuit and a delay circuit, along with a specific configuration of transistors in the output circuit, optimizing the current drive capabilities of transistors to minimize duty ratio deviations by ensuring consistent timing changes for both rising and falling edge transitions of the input signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple inverter circuit is used to increase signal amplitude, then the circuit complexity is reduced, but timing differences occur between logic level transitions causing duty ratio deviation
Solution Approach 1:
The patent applies preliminary action by introducing a delay circuit that pre-adjusts the timing of one of the control signals before it reaches the output transistor. The delay circuit compensates for the inherent timing differences in the inverter circuit, ensuring that both rising and falling edge transitions occur at consistent times. This preliminary timing adjustment prevents duty ratio deviation while maintaining the simplicity of the overall circuit structure.
2Manufacturing precision
If cross-coupled transistors are used to increase signal amplitude, then timing differences between logic transitions are reduced, but the circuit complexity increases
Solution Approach 1:
The patent segments the level shift circuit into distinct functional blocks: an inverter circuit portion and an output circuit portion with a delay circuit. This segmentation allows each portion to be optimized independently - the inverter portion handles signal inversion while the delay circuit specifically addresses timing alignment. By dividing the circuit this way, the patent achieves good duty ratio precision without requiring the more complex cross-coupled transistor configuration throughout the entire circuit.
3Device complexity
If transistor current drive capabilities are not optimized, then the circuit design is simpler, but timing consistency between rising and falling edges deteriorates
Solution Approach 1:
The patent applies parameter changes by adjusting the current drive capabilities of specific transistors in the output circuit. The delay circuit is designed with transistor parameters (such as width-to-length ratios) that are optimized to provide the appropriate delay amount. By changing these transistor parameters, the patent achieves consistent timing for both rising and falling edges while keeping the overall circuit design relatively simple and avoiding the need for complex cross-coupled configurations.
Data Source
AI summary
Disclosed herein is a device includes: a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and outputting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and outputting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.