Level Shift Circuit with Drive Adjustment for Duty Ratio Skew
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Solution Overview
Problem
Semiconductor devices face reduced operation margins due to significant deviations in the duty ratio of output voltage caused by differing delay times in the rising and falling edges of the output voltage, which existing level shift circuits fail to adequately address.
Innovation Solution
The proposed level shift circuit employs CMOS inverters and driving adjustment circuits with P-channel and N-channel field-effect transistors, where the second power supply voltage is set lower than the first, and driving adjustment circuits adjust the current driving force of low-level outputs to compensate for delay time discrepancies between rising and falling edges, thereby reducing skew attributed to process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shift circuits are used, then power supply voltage level shifting is achieved, but delay time differences between rising and falling edges cause significant duty ratio deviation
Solution Approach 1:
The patent changes the electrical parameters of the circuit by introducing adjustable current driving forces for the low level output through driving adjustment circuits. By modifying the current parameters independently for rising and falling edges, the circuit compensates for delay time differences and corrects duty ratio deviation, thereby improving both reliability and manufacturing precision.
2Device complexity
If single power supply voltage is used, then circuit design is simplified, but internal circuit characteristics cannot be well balanced through level shifting
Solution Approach 1:
The patent segments the power supply system into two distinct power supply voltages (first power supply voltage and second power supply voltage). This segmentation allows independent optimization of different circuit stages, enabling proper level shifting to balance internal circuit characteristics while maintaining a relatively simple overall structure.
3Device complexity
If delay time differences are not compensated, then circuit structure remains simple, but duty ratio deviation significantly reduces operation margin
Solution Approach 1:
The patent introduces driving adjustment circuits as intermediary components between the CMOS inverters and the output. These intermediary circuits adjust the current driving forces to compensate for delay time differences, thereby correcting duty ratio deviation and improving operation margin without significantly complicating the overall circuit structure.
Data Source
AI summary
According to one embodiment, a first CMOS inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second CMOS inverter is connected to a rear stage of the first CMOS inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first CMOS inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second CMOS inverter.