Level-Shift Latch Circuit for dV/dt Noise Suppression
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Solution Overview
Problem
Conventional level-shift circuits in half-bridge systems suffer from malfunctions due to dV/dt noise, particularly caused by element variations and external noise, leading to logic inversion and increased circuit complexity.
Innovation Solution
A level-shift circuit design that includes a first and second serial circuit with resistances and switching elements, along with a latch circuit and a capacitor connecting the output terminals of these circuits to reduce impedance differences between setdrn and resdrn signals, thereby suppressing noise-induced malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level-shift circuit is used to drive high potential-side semiconductor devices, then the circuit can transmit control signals from low potential to high potential, but the circuit is susceptible to dV/dt noise causing logic inversion and malfunctions
Solution Approach 1:
A capacitor is introduced as an intermediary component connected between the setdrn and resdrn signal lines. This capacitor acts as a mediator that equalizes potential fluctuations and suppresses dV/dt noise-induced logic inversion, thereby improving signal transmission reliability without compromising the level-shifting function
Solution Approach 2:
The capacitor is configured to preemptively counteract the harmful effects of dV/dt noise before it can cause logic inversion. By being connected between the setdrn and resdrn lines, the capacitor预先 (in advance) balances potential differences and prevents noise-induced malfunctions from occurring
2Ease of manufacture
If element variations are present in the level-shift circuit, then manufacturing tolerances are accommodated, but the circuit becomes more susceptible to noise-induced malfunctions
Solution Approach 1:
The capacitor serves as a compensating intermediary that mitigates the adverse effects of element variations. By equalizing potential fluctuations between setdrn and resdrn lines, the capacitor compensates for manufacturing tolerances while simultaneously improving noise immunity
3Object-affected harmful factors
If a latch malfunction protection circuit is added to prevent dV/dt noise effects, then noise immunity is improved, but the circuit complexity increases
Solution Approach 1:
Instead of adding a complex latch malfunction protection circuit, a simple capacitor is used as an intermediary component. This capacitor provides dV/dt noise immunity through its inherent charge-storage and potential-equalizing properties, achieving noise resistance with minimal circuit complexity
Solution Approach 2:
The invention changes the electrical parameters (potential fluctuations) between setdrn and resdrn lines by introducing the capacitor. This parameter change approach suppresses dV/dt noise effects without requiring additional complex control logic or protection circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively suppresses malfunctions caused by ON/OFF noise and external dV/dt noise, allowing for a compact latch malfunction protection circuit with improved reliability.
Implementation Method 1
a capacitor equalizing potentials between a setdrn signal line and a resdrn signal line
Implementation Method 2
a first switching element in series with a first resistance, a second switching element in series with a second resistance
Data Source
AI summary
The present invention provides a level-shift circuit that can suppress the malfunction caused by the noise due to the ON/OFF of a level-shift transistor and the dV/dt noise due to external noise. The present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side, comprising: a first serial circuit a first resistance including serially-connected to a first switching element; a second serial circuit including a second resistance serially-connected to a second switching element; a latch malfunction protection circuit for which the respective output terminals of the first and second serial circuits are connected to an input terminal; a latch circuit for receiving a signal outputted from the latch malfunction protection circuit; and a capacitor connected between drain terminals of the first resistance and the first switching element and between drain terminals of the second resistance and the second switching element.