Level Shift Circuit With dV/dt Noise Timing Protection
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Solution Overview
Problem
Conventional level shift circuits in half-bridge circuits suffer from malfunctioning due to dV/dt noise, particularly when there are manufacturing variations in parasitic capacitances, leading to incorrect timing changes in signal levels at junctions, which can result in erroneous switching operations.
Innovation Solution
A level shift circuit with a dV/dt period detection circuit that adjusts transistor impedances and logical AND circuits to manage signal levels and prevent latch malfunctions, ensuring that the high-side switching element is not erroneously turned on or off by prolonged dV/dt noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shift circuits are used in half-bridge circuits, then the circuit can operate with high-side and low-side switching elements, but the circuit malfunctions due to dV/dt noise when there are manufacturing variations in parasitic capacitances
Solution Approach 1:
The patent introduces a latch malfunction protection circuit as an intermediary between the level shift circuit and the high-side driver. This protection circuit includes detection circuits that monitor the timing of signal level changes at junctions, and control circuits that adjust transistor impedances based on detected timing differences. The intermediary protection circuit mediates the harmful dV/dt noise effects by detecting timing variations caused by parasitic capacitance variations and compensating for them through impedance adjustment, thereby preventing latch malfunctions and erroneous switching operations.
2Manufacturing precision
If manufacturing variations in parasitic capacitances occur, then the signal level timing at junctions changes incorrectly, but this leads to erroneous switching operations of the high-side switching element
Solution Approach 1:
The patent implements feedback mechanisms through detection circuits that continuously monitor the timing of signal level changes at the junctions of the level shift circuit. When timing differences exceeding a predetermined threshold are detected (indicating incorrect timing due to parasitic capacitance variations), the feedback control circuits adjust the impedances of transistors in the level shift circuit to compensate for the timing errors. This feedback loop ensures that switching operations remain accurate despite manufacturing variations in parasitic capacitances.
Solution Approach 2:
The patent dynamically changes the impedance parameters of transistors within the level shift circuit based on detected timing conditions. When incorrect timing is detected, the control circuits adjust the impedance values of specific transistors to compensate for the timing errors caused by parasitic capacitance variations. This parameter adjustment allows the circuit to adapt to manufacturing variations and maintain reliable operation without requiring precise manufacturing tolerances.
3Device complexity
If the level shift circuit is simplified without protection mechanisms, then the device complexity is reduced, but the circuit becomes susceptible to latch malfunctions from dV/dt noise
Solution Approach 1:
The patent segments the level shift circuit into functionally distinct modules: the basic level shift circuit for signal level conversion, detection circuits for monitoring timing conditions, control circuits for impedance adjustment, and a latch malfunction protection circuit for overall coordination. This segmentation allows the protection functionality to be added as a modular addition rather than fundamentally redesigning the entire level shift circuit, thereby limiting the increase in device complexity while significantly improving reliability against latch malfunctions.
Data Source
AI summary
A level shift circuit including serially-connected first resistor and first transistor and serially-connected second resistor and second transistor, a protection circuit that receives signals at a first junction between the first resistor and the first transistor and a second junction between the second resistor and the second transistor, a latch circuit receiving an output of the protection circuit, serially-connected third and fourth transistors and serially-connected fifth and sixth transistors respectively connected in parallel to the first and second resistors, a switching time detection circuit that receives the signals at the first and second junctions and detects an occurrence of switching noise, and first and second logical AND circuits that receive outputs of the switching time detection circuit and the signals at the first and second junctions, and respectively control the fourth and sixth transistors. The third and fifth transistors are controlled by an output, or an inversion thereof, of the latch circuit.